[libav.git] / libavcodec / ppc / dsputil_ppc.c

/*
 * Copyright (c) 2002 Brian Foley
 * Copyright (c) 2002 Dieter Shirley
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include "../dsputil.h"

#include "dsputil_ppc.h"

#ifdef HAVE_ALTIVEC
#include "dsputil_altivec.h"
#endif

extern void idct_put_altivec(uint8_t *dest, int line_size, int16_t *block);
extern void idct_add_altivec(uint8_t *dest, int line_size, int16_t *block);

int mm_flags = 0;

int mm_support(void)
{
    int result = 0;
#if HAVE_ALTIVEC
    if (has_altivec()) {
        result |= MM_ALTIVEC;
    }
#endif /* result */
    return result;
}

#ifdef POWERPC_TBL_PERFORMANCE_REPORT
unsigned long long perfdata[powerpc_perf_total][powerpc_data_total];
/* list below must match enum in dsputil_ppc.h */
static unsigned char* perfname[] = {
  "fft_calc_altivec",
  "gmc1_altivec",
  "dct_unquantize_h263_altivec",
  "idct_add_altivec",
  "idct_put_altivec",
  "put_pixels16_altivec",
  "avg_pixels16_altivec",
  "avg_pixels8_altivec",
  "put_pixels8_xy2_altivec",
  "put_no_rnd_pixels8_xy2_altivec",
  "put_pixels16_xy2_altivec",
  "put_no_rnd_pixels16_xy2_altivec",
  "clear_blocks_dcbz32_ppc",
  "clear_blocks_dcbz128_ppc"
};
#ifdef POWERPC_PERF_USE_PMC
unsigned long long perfdata_miss[powerpc_perf_total][powerpc_data_total];
#endif
#include <stdio.h>
#endif

#ifdef POWERPC_TBL_PERFORMANCE_REPORT
void powerpc_display_perf_report(void)
{
  int i;
#ifndef POWERPC_PERF_USE_PMC
  fprintf(stderr, "PowerPC performance report\n Values are from the Time Base register, and represent 4 bus cycles.\n");
#else /* POWERPC_PERF_USE_PMC */
  fprintf(stderr, "PowerPC performance report\n Values are from the PMC registers, and represent whatever the registers are set to record.\n");
#endif /* POWERPC_PERF_USE_PMC */
  for(i = 0 ; i < powerpc_perf_total ; i++)
  {
    if (perfdata[i][powerpc_data_num] != (unsigned long long)0)
      fprintf(stderr, " Function \"%s\" (pmc1):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n",
              perfname[i],
              perfdata[i][powerpc_data_min],
              perfdata[i][powerpc_data_max],
              (double)perfdata[i][powerpc_data_sum] /
              (double)perfdata[i][powerpc_data_num],
              perfdata[i][powerpc_data_num]);
#ifdef POWERPC_PERF_USE_PMC
    if (perfdata_miss[i][powerpc_data_num] != (unsigned long long)0)
      fprintf(stderr, " Function \"%s\" (pmc2):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n",
              perfname[i],
              perfdata_miss[i][powerpc_data_min],
              perfdata_miss[i][powerpc_data_max],
              (double)perfdata_miss[i][powerpc_data_sum] /
              (double)perfdata_miss[i][powerpc_data_num],
              perfdata_miss[i][powerpc_data_num]);
#endif
  }
}
#endif /* POWERPC_TBL_PERFORMANCE_REPORT */

/* ***** WARNING ***** WARNING ***** WARNING ***** */
/*
  clear_blocks_dcbz32_ppc will not work properly
  on PowerPC processors with a cache line size
  not equal to 32 bytes.
  Fortunately all processor used by Apple up to
  at least the 7450 (aka second generation G4)
  use 32 bytes cache line.
  This is due to the use of the 'dcbz' instruction.
  It simply clear to zero a single cache line,
  so you need to know the cache line size to use it !
  It's absurd, but it's fast...

  update 24/06/2003 : Apple released yesterday the G5,
  with a PPC970. cache line size : 128 bytes. Oups.
  The semantic of dcbz was changed, it always clear
  32 bytes. so the function below will work, but will
  be slow. So I fixed check_dcbz_effect to use dcbzl,
  which is defined to clear a cache line (as dcbz before).
  So we still can distinguish, and use dcbz (32 bytes)
  or dcbzl (one cache line) as required.

  see <http://developer.apple.com/technotes/tn/tn2087.html>
  and <http://developer.apple.com/technotes/tn/tn2086.html>
*/
void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
{
POWERPC_TBL_DECLARE(powerpc_clear_blocks_dcbz32, 1);
    register int misal = ((unsigned long)blocks & 0x00000010);
    register int i = 0;
POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz32, 1);
#if 1
    if (misal) {
      ((unsigned long*)blocks)[0] = 0L;
      ((unsigned long*)blocks)[1] = 0L;
      ((unsigned long*)blocks)[2] = 0L;
      ((unsigned long*)blocks)[3] = 0L;
      i += 16;
    }
    for ( ; i < sizeof(DCTELEM)*6*64 ; i += 32) {
      asm volatile("dcbz %0,%1" : : "r" (i), "r" (blocks) : "memory");
    }
    if (misal) {
      ((unsigned long*)blocks)[188] = 0L;
      ((unsigned long*)blocks)[189] = 0L;
      ((unsigned long*)blocks)[190] = 0L;
      ((unsigned long*)blocks)[191] = 0L;
      i += 16;
    }
#else
    memset(blocks, 0, sizeof(DCTELEM)*6*64);
#endif
POWERPC_TBL_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1);
}

/* same as above, when dcbzl clear a whole 128B cache line
   i.e. the PPC970 aka G5 */
#ifndef NO_DCBZL
void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
{
POWERPC_TBL_DECLARE(powerpc_clear_blocks_dcbz128, 1);
    register int misal = ((unsigned long)blocks & 0x0000007f);
    register int i = 0;
POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz128, 1);
#if 1
 if (misal) {
   // we could probably also optimize this case,
   // but there's not much point as the machines
   // aren't available yet (2003-06-26)
      memset(blocks, 0, sizeof(DCTELEM)*6*64);
    }
    else
      for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
	asm volatile("dcbzl %0,%1" : : "r" (i), "r" (blocks) : "memory");
      }
#else
    memset(blocks, 0, sizeof(DCTELEM)*6*64);
#endif
POWERPC_TBL_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1);
}
#else
void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
{
  memset(blocks, 0, sizeof(DCTELEM)*6*64);
}
#endif

#ifndef NO_DCBZL
/* check dcbz report how many bytes are set to 0 by dcbz */
/* update 24/06/2003 : replace dcbz by dcbzl to get
   the intended effect (Apple "fixed" dcbz)
   unfortunately this cannot be used unless the assembler
   knows about dcbzl ... */
long check_dcbzl_effect(void)
{
  register char *fakedata = (char*)av_malloc(1024);
  register char *fakedata_middle;
  register long zero = 0;
  register long i = 0;
  long count = 0;

  if (!fakedata)
  {
    return 0L;
  }

  fakedata_middle = (fakedata + 512);

  memset(fakedata, 0xFF, 1024);

  asm volatile("dcbzl %0, %1" : : "r" (fakedata_middle), "r" (zero));

  for (i = 0; i < 1024 ; i ++)
  {
    if (fakedata[i] == (char)0)
      count++;
  }

  av_free(fakedata);
  
  return count;
}
#else
long check_dcbzl_effect(void)
{
  return 0;
}
#endif

void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
{
    // Common optimizations whether Altivec is available or not

  switch (check_dcbzl_effect()) {
  case 32:
    c->clear_blocks = clear_blocks_dcbz32_ppc;
    break;
  case 128:
    c->clear_blocks = clear_blocks_dcbz128_ppc;
    break;
  default:
    break;
  }
  
#if HAVE_ALTIVEC
    if (has_altivec()) {
        mm_flags |= MM_ALTIVEC;
        
        // Altivec specific optimisations
        c->pix_abs16x16_x2 = pix_abs16x16_x2_altivec;
        c->pix_abs16x16_y2 = pix_abs16x16_y2_altivec;
        c->pix_abs16x16_xy2 = pix_abs16x16_xy2_altivec;
        c->pix_abs16x16 = pix_abs16x16_altivec;
        c->pix_abs8x8 = pix_abs8x8_altivec;
        c->sad[0]= sad16x16_altivec;
        c->sad[1]= sad8x8_altivec;
        c->pix_norm1 = pix_norm1_altivec;
        c->sse[1]= sse8_altivec;
        c->sse[0]= sse16_altivec;
        c->pix_sum = pix_sum_altivec;
        c->diff_pixels = diff_pixels_altivec;
        c->get_pixels = get_pixels_altivec;
// next one disabled as it's untested.
#if 0
        c->add_bytes= add_bytes_altivec;
#endif /* 0 */
        c->put_pixels_tab[0][0] = put_pixels16_altivec;
        c->avg_pixels_tab[0][0] = avg_pixels16_altivec;
// next one disabled as it's untested.
#if 0
        c->avg_pixels_tab[1][0] = avg_pixels8_altivec;
#endif /* 0 */
        c->put_pixels_tab[1][3] = put_pixels8_xy2_altivec;
        c->put_no_rnd_pixels_tab[1][3] = put_no_rnd_pixels8_xy2_altivec;
        c->put_pixels_tab[0][3] = put_pixels16_xy2_altivec;
        c->put_no_rnd_pixels_tab[0][3] = put_no_rnd_pixels16_xy2_altivec;
        
	c->gmc1 = gmc1_altivec;

        if ((avctx->idct_algo == FF_IDCT_AUTO) ||
                (avctx->idct_algo == FF_IDCT_ALTIVEC))
        {
            c->idct_put = idct_put_altivec;
            c->idct_add = idct_add_altivec;
#ifndef ALTIVEC_USE_REFERENCE_C_CODE
            c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
#else /* ALTIVEC_USE_REFERENCE_C_CODE */
            c->idct_permutation_type = FF_NO_IDCT_PERM;
#endif /* ALTIVEC_USE_REFERENCE_C_CODE */
        }
        
#ifdef POWERPC_TBL_PERFORMANCE_REPORT
        {
          int i;
          for (i = 0 ; i < powerpc_perf_total ; i++)
          {
            perfdata[i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFF;
            perfdata[i][powerpc_data_max] = 0x0000000000000000;
            perfdata[i][powerpc_data_sum] = 0x0000000000000000;
            perfdata[i][powerpc_data_num] = 0x0000000000000000;
#ifdef POWERPC_PERF_USE_PMC
            perfdata_miss[i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFF;
            perfdata_miss[i][powerpc_data_max] = 0x0000000000000000;
            perfdata_miss[i][powerpc_data_sum] = 0x0000000000000000;
            perfdata_miss[i][powerpc_data_num] = 0x0000000000000000;
#endif /* POWERPC_PERF_USE_PMC */
          }
        }
#endif /* POWERPC_TBL_PERFORMANCE_REPORT */
    } else
#endif /* HAVE_ALTIVEC */
    {
        // Non-AltiVec PPC optimisations

        // ... pending ...
    }
}
Commit	Line	Data
05c4072b MN	1	/*
	2	* Copyright (c) 2002 Brian Foley
	3	* Copyright (c) 2002 Dieter Shirley
	4	*
	5	* This library is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU Lesser General Public
	7	* License as published by the Free Software Foundation; either
	8	* version 2 of the License, or (at your option) any later version.
	9	*
	10	* This library is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* Lesser General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU Lesser General Public
	16	* License along with this library; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
ab6c65f6 BF	20	#include "../dsputil.h"
ab6c65f6 BF	21
35e5fb06 RD	22	#include "dsputil_ppc.h"
35e5fb06 RD	23
ab6c65f6 BF	24	#ifdef HAVE_ALTIVEC
	25	#include "dsputil_altivec.h"
	26	#endif
	27
b0368839 MN	28	extern void idct_put_altivec(uint8_t dest, int line_size, int16_t block);
	29	extern void idct_add_altivec(uint8_t dest, int line_size, int16_t block);
	30
404d2241 BF	31	int mm_flags = 0;
404d2241 BF	32
e629ab68 RD	33	int mm_support(void)
	34	{
	35	int result = 0;
	36	#if HAVE_ALTIVEC
	37	if (has_altivec()) {
	38	result \|= MM_ALTIVEC;
	39	}
	40	#endif /* result */
	41	return result;
	42	}
	43
35e5fb06 RD	44	#ifdef POWERPC_TBL_PERFORMANCE_REPORT
35e5fb06 RD	45	unsigned long long perfdata[powerpc_perf_total][powerpc_data_total];
fe50f385	46	/* list below must match enum in dsputil_ppc.h */
35e5fb06 RD	47	static unsigned char* perfname[] = {
	48	"fft_calc_altivec",
	49	"gmc1_altivec",
	50	"dct_unquantize_h263_altivec",
	51	"idct_add_altivec",
	52	"idct_put_altivec",
35e5fb06 RD	53	"put_pixels16_altivec",
	54	"avg_pixels16_altivec",
	55	"avg_pixels8_altivec",
	56	"put_pixels8_xy2_altivec",
fe50f385 RD	57	"put_no_rnd_pixels8_xy2_altivec",
	58	"put_pixels16_xy2_altivec",
	59	"put_no_rnd_pixels16_xy2_altivec",
a4adb608 MN	60	"clear_blocks_dcbz32_ppc",
a4adb608 MN	61	"clear_blocks_dcbz128_ppc"
35e5fb06 RD	62	};
	63	#ifdef POWERPC_PERF_USE_PMC
	64	unsigned long long perfdata_miss[powerpc_perf_total][powerpc_data_total];
	65	#endif
	66	#include <stdio.h>
	67	#endif
	68
	69	#ifdef POWERPC_TBL_PERFORMANCE_REPORT
	70	void powerpc_display_perf_report(void)
	71	{
	72	int i;
	73	#ifndef POWERPC_PERF_USE_PMC
fe50f385	74	fprintf(stderr, "PowerPC performance report\n Values are from the Time Base register, and represent 4 bus cycles.\n");
35e5fb06	75	#else /* POWERPC_PERF_USE_PMC */
fe50f385	76	fprintf(stderr, "PowerPC performance report\n Values are from the PMC registers, and represent whatever the registers are set to record.\n");
35e5fb06 RD	77	#endif /* POWERPC_PERF_USE_PMC */
	78	for(i = 0 ; i < powerpc_perf_total ; i++)
	79	{
	80	if (perfdata[i][powerpc_data_num] != (unsigned long long)0)
	81	fprintf(stderr, " Function \"%s\" (pmc1):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n",
	82	perfname[i],
	83	perfdata[i][powerpc_data_min],
	84	perfdata[i][powerpc_data_max],
	85	(double)perfdata[i][powerpc_data_sum] /
	86	(double)perfdata[i][powerpc_data_num],
	87	perfdata[i][powerpc_data_num]);
	88	#ifdef POWERPC_PERF_USE_PMC
	89	if (perfdata_miss[i][powerpc_data_num] != (unsigned long long)0)
	90	fprintf(stderr, " Function \"%s\" (pmc2):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n",
	91	perfname[i],
	92	perfdata_miss[i][powerpc_data_min],
	93	perfdata_miss[i][powerpc_data_max],
	94	(double)perfdata_miss[i][powerpc_data_sum] /
	95	(double)perfdata_miss[i][powerpc_data_num],
	96	perfdata_miss[i][powerpc_data_num]);
	97	#endif
	98	}
	99	}
	100	#endif /* POWERPC_TBL_PERFORMANCE_REPORT */
	101
	102	/* *** WARNING * WARNING * WARNING *** */
	103	/*
	104	clear_blocks_dcbz32_ppc will not work properly
	105	on PowerPC processors with a cache line size
	106	not equal to 32 bytes.
	107	Fortunately all processor used by Apple up to
	108	at least the 7450 (aka second generation G4)
	109	use 32 bytes cache line.
	110	This is due to the use of the 'dcbz' instruction.
	111	It simply clear to zero a single cache line,
	112	so you need to know the cache line size to use it !
	113	It's absurd, but it's fast...
a4adb608 MN	114
	115	update 24/06/2003 : Apple released yesterday the G5,
	116	with a PPC970. cache line size : 128 bytes. Oups.
	117	The semantic of dcbz was changed, it always clear
	118	32 bytes. so the function below will work, but will
	119	be slow. So I fixed check_dcbz_effect to use dcbzl,
	120	which is defined to clear a cache line (as dcbz before).
	121	So we still can distinguish, and use dcbz (32 bytes)
	122	or dcbzl (one cache line) as required.
	123
	124	see <http://developer.apple.com/technotes/tn/tn2087.html>
	125	and <http://developer.apple.com/technotes/tn/tn2086.html>
35e5fb06 RD	126	*/
	127	void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
	128	{
	129	POWERPC_TBL_DECLARE(powerpc_clear_blocks_dcbz32, 1);
	130	register int misal = ((unsigned long)blocks & 0x00000010);
	131	register int i = 0;
	132	POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz32, 1);
	133	#if 1
	134	if (misal) {
	135	((unsigned long*)blocks)[0] = 0L;
	136	((unsigned long*)blocks)[1] = 0L;
	137	((unsigned long*)blocks)[2] = 0L;
	138	((unsigned long*)blocks)[3] = 0L;
35e5fb06 RD	139	i += 16;
	140	}
	141	for ( ; i < sizeof(DCTELEM)664 ; i += 32) {
a4adb608	142	asm volatile("dcbz %0,%1" : : "r" (i), "r" (blocks) : "memory");
35e5fb06 RD	143	}
	144	if (misal) {
	145	((unsigned long*)blocks)[188] = 0L;
	146	((unsigned long*)blocks)[189] = 0L;
	147	((unsigned long*)blocks)[190] = 0L;
	148	((unsigned long*)blocks)[191] = 0L;
	149	i += 16;
	150	}
	151	#else
	152	memset(blocks, 0, sizeof(DCTELEM)664);
	153	#endif
	154	POWERPC_TBL_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1);
	155	}
	156
a4adb608 MN	157	/* same as above, when dcbzl clear a whole 128B cache line
	158	i.e. the PPC970 aka G5 */
	159	#ifndef NO_DCBZL
	160	void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
	161	{
	162	POWERPC_TBL_DECLARE(powerpc_clear_blocks_dcbz128, 1);
	163	register int misal = ((unsigned long)blocks & 0x0000007f);
	164	register int i = 0;
	165	POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz128, 1);
	166	#if 1
	167	if (misal) {
	168	// we could probably also optimize this case,
	169	// but there's not much point as the machines
	170	// aren't available yet (2003-06-26)
	171	memset(blocks, 0, sizeof(DCTELEM)664);
	172	}
	173	else
	174	for ( ; i < sizeof(DCTELEM)664 ; i += 128) {
	175	asm volatile("dcbzl %0,%1" : : "r" (i), "r" (blocks) : "memory");
	176	}
	177	#else
	178	memset(blocks, 0, sizeof(DCTELEM)664);
	179	#endif
	180	POWERPC_TBL_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1);
	181	}
	182	#else
	183	void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
	184	{
	185	memset(blocks, 0, sizeof(DCTELEM)664);
	186	}
	187	#endif
	188
	189	#ifndef NO_DCBZL
35e5fb06	190	/* check dcbz report how many bytes are set to 0 by dcbz */
a4adb608 MN	191	/* update 24/06/2003 : replace dcbz by dcbzl to get
	192	the intended effect (Apple "fixed" dcbz)
	193	unfortunately this cannot be used unless the assembler
	194	knows about dcbzl ... */
	195	long check_dcbzl_effect(void)
35e5fb06	196	{
3b991c54	197	register char fakedata = (char)av_malloc(1024);
35e5fb06 RD	198	register char *fakedata_middle;
	199	register long zero = 0;
	200	register long i = 0;
	201	long count = 0;
	202
3b991c54	203	if (!fakedata)
35e5fb06 RD	204	{
	205	return 0L;
	206	}
	207
35e5fb06 RD	208	fakedata_middle = (fakedata + 512);
	209
	210	memset(fakedata, 0xFF, 1024);
	211
a4adb608	212	asm volatile("dcbzl %0, %1" : : "r" (fakedata_middle), "r" (zero));
35e5fb06 RD	213
	214	for (i = 0; i < 1024 ; i ++)
	215	{
	216	if (fakedata[i] == (char)0)
	217	count++;
	218	}
	219
3b991c54	220	av_free(fakedata);
35e5fb06 RD	221
	222	return count;
	223	}
a4adb608 MN	224	#else
	225	long check_dcbzl_effect(void)
	226	{
	227	return 0;
	228	}
	229	#endif
35e5fb06	230
b0368839	231	void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
ab6c65f6	232	{
a4adb608	233	// Common optimizations whether Altivec is available or not
05c4072b	234
a4adb608	235	switch (check_dcbzl_effect()) {
35e5fb06 RD	236	case 32:
	237	c->clear_blocks = clear_blocks_dcbz32_ppc;
	238	break;
a4adb608 MN	239	case 128:
	240	c->clear_blocks = clear_blocks_dcbz128_ppc;
	241	break;
35e5fb06 RD	242	default:
	243	break;
	244	}
	245
ab6c65f6 BF	246	#if HAVE_ALTIVEC
ab6c65f6 BF	247	if (has_altivec()) {
404d2241 BF	248	mm_flags \|= MM_ALTIVEC;
404d2241 BF	249
05c4072b	250	// Altivec specific optimisations
f2677d6b BF	251	c->pix_abs16x16_x2 = pix_abs16x16_x2_altivec;
f2677d6b BF	252	c->pix_abs16x16_y2 = pix_abs16x16_y2_altivec;
9c76bd48 BF	253	c->pix_abs16x16_xy2 = pix_abs16x16_xy2_altivec;
9c76bd48 BF	254	c->pix_abs16x16 = pix_abs16x16_altivec;
af19f78f	255	c->pix_abs8x8 = pix_abs8x8_altivec;
e629ab68 RD	256	c->sad[0]= sad16x16_altivec;
e629ab68 RD	257	c->sad[1]= sad8x8_altivec;
f2677d6b	258	c->pix_norm1 = pix_norm1_altivec;
4013fcf4 FB	259	c->sse[1]= sse8_altivec;
4013fcf4 FB	260	c->sse[0]= sse16_altivec;
af19f78f ZK	261	c->pix_sum = pix_sum_altivec;
	262	c->diff_pixels = diff_pixels_altivec;
	263	c->get_pixels = get_pixels_altivec;
fe50f385	264	// next one disabled as it's untested.
e629ab68 RD	265	#if 0
e629ab68 RD	266	c->add_bytes= add_bytes_altivec;
fe50f385	267	#endif /* 0 */
db40a39a MN	268	c->put_pixels_tab[0][0] = put_pixels16_altivec;
db40a39a MN	269	c->avg_pixels_tab[0][0] = avg_pixels16_altivec;
35e5fb06 RD	270	// next one disabled as it's untested.
	271	#if 0
	272	c->avg_pixels_tab[1][0] = avg_pixels8_altivec;
fe50f385	273	#endif /* 0 */
35e5fb06	274	c->put_pixels_tab[1][3] = put_pixels8_xy2_altivec;
fe50f385 RD	275	c->put_no_rnd_pixels_tab[1][3] = put_no_rnd_pixels8_xy2_altivec;
	276	c->put_pixels_tab[0][3] = put_pixels16_xy2_altivec;
	277	c->put_no_rnd_pixels_tab[0][3] = put_no_rnd_pixels16_xy2_altivec;
35e5fb06	278
e629ab68	279	c->gmc1 = gmc1_altivec;
b0368839 MN	280
	281	if ((avctx->idct_algo == FF_IDCT_AUTO) \|\|
	282	(avctx->idct_algo == FF_IDCT_ALTIVEC))
	283	{
	284	c->idct_put = idct_put_altivec;
	285	c->idct_add = idct_add_altivec;
	286	#ifndef ALTIVEC_USE_REFERENCE_C_CODE
	287	c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
	288	#else /* ALTIVEC_USE_REFERENCE_C_CODE */
	289	c->idct_permutation_type = FF_NO_IDCT_PERM;
	290	#endif /* ALTIVEC_USE_REFERENCE_C_CODE */
	291	}
fe50f385	292
35e5fb06	293	#ifdef POWERPC_TBL_PERFORMANCE_REPORT
db40a39a MN	294	{
db40a39a MN	295	int i;
35e5fb06	296	for (i = 0 ; i < powerpc_perf_total ; i++)
db40a39a	297	{
35e5fb06 RD	298	perfdata[i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFF;
	299	perfdata[i][powerpc_data_max] = 0x0000000000000000;
	300	perfdata[i][powerpc_data_sum] = 0x0000000000000000;
	301	perfdata[i][powerpc_data_num] = 0x0000000000000000;
	302	#ifdef POWERPC_PERF_USE_PMC
	303	perfdata_miss[i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFF;
	304	perfdata_miss[i][powerpc_data_max] = 0x0000000000000000;
	305	perfdata_miss[i][powerpc_data_sum] = 0x0000000000000000;
	306	perfdata_miss[i][powerpc_data_num] = 0x0000000000000000;
fe50f385	307	#endif /* POWERPC_PERF_USE_PMC */
db40a39a MN	308	}
db40a39a MN	309	}
fe50f385	310	#endif /* POWERPC_TBL_PERFORMANCE_REPORT */
ab6c65f6	311	} else
fe50f385	312	#endif /* HAVE_ALTIVEC */
ab6c65f6	313	{
05c4072b MN	314	// Non-AltiVec PPC optimisations
	315
	316	// ... pending ...
ab6c65f6 BF	317	}
ab6c65f6 BF	318	}