x86inc: Preserve arguments when allocating stack space
[libav.git] / libavutil / x86 / x86inc.asm
CommitLineData
bafad220 1;*****************************************************************************
2f7f2e4b 2;* x86inc.asm: x264asm abstraction layer
bafad220 3;*****************************************************************************
715eb7ca 4;* Copyright (C) 2005-2016 x264 project
bafad220 5;*
2966cc18
JGG
6;* Authors: Loren Merritt <lorenm@u.washington.edu>
7;* Anton Mitrofanov <BugMaster@narod.ru>
79793f83 8;* Fiona Glaser <fiona@x264.com>
ad7d7d4f 9;* Henrik Gramner <henrik@gramner.com>
bafad220 10;*
2966cc18
JGG
11;* Permission to use, copy, modify, and/or distribute this software for any
12;* purpose with or without fee is hereby granted, provided that the above
13;* copyright notice and this permission notice appear in all copies.
bafad220 14;*
2966cc18
JGG
15;* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
16;* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17;* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
18;* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
19;* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
20;* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
21;* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
bafad220
LM
22;*****************************************************************************
23
2966cc18
JGG
24; This is a header file for the x264ASM assembly language, which uses
25; NASM/YASM syntax combined with a large number of macros to provide easy
26; abstraction between different calling conventions (x86_32, win64, linux64).
27; It also has various other useful features to simplify writing the kind of
28; DSP functions that are most often used in x264.
29
30; Unlike the rest of x264, this file is available under an ISC license, as it
31; has significant usefulness outside of x264 and we want it to be available
32; to the largest audience possible. Of course, if you modify it for your own
33; purposes to add a new feature, we strongly encourage contributing a patch
34; as this feature might be useful for others as well. Send patches or ideas
35; to x264-devel@videolan.org .
36
ef5d41a5
DB
37%ifndef private_prefix
38 %define private_prefix x264
012f73e2 39%endif
2966cc18 40
d633d12b
DB
41%ifndef public_prefix
42 %define public_prefix private_prefix
43%endif
44
9f1245eb
HG
45%if HAVE_ALIGNED_STACK
46 %define STACK_ALIGNMENT 16
47%endif
48%ifndef STACK_ALIGNMENT
49 %if ARCH_X86_64
50 %define STACK_ALIGNMENT 16
51 %else
52 %define STACK_ALIGNMENT 4
53 %endif
54%endif
55
3b15a6d7 56%define WIN64 0
96c9cc10 57%define UNIX64 0
3b15a6d7 58%if ARCH_X86_64
3f87f39c 59 %ifidn __OUTPUT_FORMAT__,win32
3b15a6d7 60 %define WIN64 1
166f3993
HY
61 %elifidn __OUTPUT_FORMAT__,win64
62 %define WIN64 1
47f9d7ce
DB
63 %elifidn __OUTPUT_FORMAT__,x64
64 %define WIN64 1
3f87f39c 65 %else
3b15a6d7 66 %define UNIX64 1
3f87f39c
JA
67 %endif
68%endif
69
44b44441
HG
70%define FORMAT_ELF 0
71%ifidn __OUTPUT_FORMAT__,elf
72 %define FORMAT_ELF 1
73%elifidn __OUTPUT_FORMAT__,elf32
74 %define FORMAT_ELF 1
75%elifidn __OUTPUT_FORMAT__,elf64
76 %define FORMAT_ELF 1
77%endif
78
2966cc18
JGG
79%ifdef PREFIX
80 %define mangle(x) _ %+ x
81%else
82 %define mangle(x) x
83%endif
84
ad7d7d4f
HG
85; aout does not support align=
86; NOTE: This section is out of sync with x264, in order to
87; keep supporting OS/2.
3f87f39c 88%macro SECTION_RODATA 0-1 16
ad7d7d4f 89 %ifidn __OUTPUT_FORMAT__,aout
d69f9a42 90 section .text
bafad220 91 %else
3f87f39c 92 SECTION .rodata align=%1
bafad220
LM
93 %endif
94%endmacro
95
3b15a6d7 96%if WIN64
3f87f39c 97 %define PIC
412b248e 98%elif ARCH_X86_64 == 0
2966cc18
JGG
99; x86_32 doesn't require PIC.
100; Some distros prefer shared objects to be PIC, but nothing breaks if
101; the code contains a few textrels, so we'll skip that complexity.
3f87f39c
JA
102 %undef PIC
103%endif
104%ifdef PIC
2966cc18 105 default rel
bafad220
LM
106%endif
107
180d43bc
MR
108%macro CPUNOP 1
109 %if HAVE_CPUNOP
110 CPU %1
111 %endif
112%endmacro
113
bafad220
LM
114; Macros to eliminate most code duplication between x86_32 and x86_64:
115; Currently this works only for leaf functions which load all their arguments
116; into registers at the start, and make no other use of the stack. Luckily that
117; covers most of x264's asm.
118
119; PROLOGUE:
120; %1 = number of arguments. loads them from stack if needed.
3f87f39c
JA
121; %2 = number of registers used. pushes callee-saved regs if needed.
122; %3 = number of xmm registers used. pushes callee-saved xmm regs if needed.
9f1245eb
HG
123; %4 = (optional) stack size to be allocated. The stack will be aligned before
124; allocating the specified stack size. If the required stack alignment is
125; larger than the known stack alignment the stack will be manually aligned
6f40e9f0
RB
126; and an extra register will be allocated to hold the original stack
127; pointer (to not invalidate r0m etc.). To prevent the use of an extra
128; register as stack pointer, request a negative stack size.
129; %4+/%5+ = list of names to define to registers
bafad220
LM
130; PROLOGUE can also be invoked by adding the same options to cglobal
131
132; e.g.
9f1245eb
HG
133; cglobal foo, 2,3,7,0x40, dst, src, tmp
134; declares a function (foo) that automatically loads two arguments (dst and
135; src) into registers, uses one additional register (tmp) plus 7 vector
136; registers (m0-m6) and allocates 0x40 bytes of stack space.
bafad220
LM
137
138; TODO Some functions can use some args directly from the stack. If they're the
139; last args then you can just not declare them, but if they're in the middle
140; we need more flexible macro.
141
142; RET:
2f7f2e4b 143; Pops anything that was pushed by PROLOGUE, and returns.
bafad220
LM
144
145; REP_RET:
25cb0c1a 146; Use this instead of RET if it's a branch target.
bafad220 147
3f87f39c
JA
148; registers:
149; rN and rNq are the native-size register holding function argument N
150; rNd, rNw, rNb are dword, word, and byte size
96c9cc10 151; rNh is the high 8 bits of the word size
3f87f39c
JA
152; rNm is the original location of arg N (a register or on the stack), dword
153; rNmp is native size
154
96c9cc10 155%macro DECLARE_REG 2-3
bafad220 156 %define r%1q %2
96c9cc10
RB
157 %define r%1d %2d
158 %define r%1w %2w
159 %define r%1b %2b
160 %define r%1h %2h
7a1944b9 161 %define %2q %2
96c9cc10
RB
162 %if %0 == 2
163 %define r%1m %2d
3f87f39c 164 %define r%1mp %2
3b15a6d7 165 %elif ARCH_X86_64 ; memory
6f40e9f0 166 %define r%1m [rstk + stack_offset + %3]
0995ad8d 167 %define r%1mp qword r %+ %1 %+ m
3f87f39c 168 %else
6f40e9f0 169 %define r%1m [rstk + stack_offset + %3]
0995ad8d 170 %define r%1mp dword r %+ %1 %+ m
3f87f39c 171 %endif
bafad220
LM
172 %define r%1 %2
173%endmacro
174
96c9cc10 175%macro DECLARE_REG_SIZE 3
bafad220
LM
176 %define r%1q r%1
177 %define e%1q r%1
178 %define r%1d e%1
179 %define e%1d e%1
180 %define r%1w %1
181 %define e%1w %1
96c9cc10
RB
182 %define r%1h %3
183 %define e%1h %3
bafad220
LM
184 %define r%1b %2
185 %define e%1b %2
3b15a6d7 186%if ARCH_X86_64 == 0
bafad220
LM
187 %define r%1 e%1
188%endif
189%endmacro
190
96c9cc10
RB
191DECLARE_REG_SIZE ax, al, ah
192DECLARE_REG_SIZE bx, bl, bh
193DECLARE_REG_SIZE cx, cl, ch
194DECLARE_REG_SIZE dx, dl, dh
195DECLARE_REG_SIZE si, sil, null
196DECLARE_REG_SIZE di, dil, null
197DECLARE_REG_SIZE bp, bpl, null
bafad220 198
3f87f39c
JA
199; t# defines for when per-arch register allocation is more complex than just function arguments
200
201%macro DECLARE_REG_TMP 1-*
202 %assign %%i 0
203 %rep %0
204 CAT_XDEFINE t, %%i, r%1
205 %assign %%i %%i+1
206 %rotate 1
207 %endrep
208%endmacro
209
210%macro DECLARE_REG_TMP_SIZE 0-*
211 %rep %0
212 %define t%1q t%1 %+ q
213 %define t%1d t%1 %+ d
214 %define t%1w t%1 %+ w
96c9cc10 215 %define t%1h t%1 %+ h
3f87f39c
JA
216 %define t%1b t%1 %+ b
217 %rotate 1
218 %endrep
219%endmacro
220
729f90e2 221DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14
3f87f39c 222
3b15a6d7 223%if ARCH_X86_64
bafad220
LM
224 %define gprsize 8
225%else
226 %define gprsize 4
227%endif
228
229%macro PUSH 1
230 push %1
6f40e9f0
RB
231 %ifidn rstk, rsp
232 %assign stack_offset stack_offset+gprsize
233 %endif
bafad220
LM
234%endmacro
235
236%macro POP 1
237 pop %1
6f40e9f0
RB
238 %ifidn rstk, rsp
239 %assign stack_offset stack_offset-gprsize
240 %endif
bafad220
LM
241%endmacro
242
729f90e2
HG
243%macro PUSH_IF_USED 1-*
244 %rep %0
245 %if %1 < regs_used
246 PUSH r%1
247 %endif
248 %rotate 1
249 %endrep
250%endmacro
251
252%macro POP_IF_USED 1-*
253 %rep %0
254 %if %1 < regs_used
255 pop r%1
256 %endif
257 %rotate 1
258 %endrep
259%endmacro
260
261%macro LOAD_IF_USED 1-*
262 %rep %0
263 %if %1 < num_args
264 mov r%1, r %+ %1 %+ mp
265 %endif
266 %rotate 1
267 %endrep
268%endmacro
269
bafad220
LM
270%macro SUB 2
271 sub %1, %2
6f40e9f0 272 %ifidn %1, rstk
bafad220
LM
273 %assign stack_offset stack_offset+(%2)
274 %endif
275%endmacro
276
277%macro ADD 2
278 add %1, %2
6f40e9f0 279 %ifidn %1, rstk
bafad220
LM
280 %assign stack_offset stack_offset-(%2)
281 %endif
282%endmacro
283
284%macro movifnidn 2
285 %ifnidn %1, %2
286 mov %1, %2
287 %endif
288%endmacro
289
290%macro movsxdifnidn 2
291 %ifnidn %1, %2
292 movsxd %1, %2
293 %endif
294%endmacro
295
296%macro ASSERT 1
297 %if (%1) == 0
f60f06d9 298 %error assertion ``%1'' failed
bafad220
LM
299 %endif
300%endmacro
301
302%macro DEFINE_ARGS 0-*
303 %ifdef n_arg_names
304 %assign %%i 0
305 %rep n_arg_names
306 CAT_UNDEF arg_name %+ %%i, q
307 CAT_UNDEF arg_name %+ %%i, d
308 CAT_UNDEF arg_name %+ %%i, w
96c9cc10 309 CAT_UNDEF arg_name %+ %%i, h
bafad220 310 CAT_UNDEF arg_name %+ %%i, b
2f77923d 311 CAT_UNDEF arg_name %+ %%i, m
98b9da2a 312 CAT_UNDEF arg_name %+ %%i, mp
bafad220
LM
313 CAT_UNDEF arg_name, %%i
314 %assign %%i %%i+1
315 %endrep
316 %endif
317
0f53d0cf
LM
318 %xdefine %%stack_offset stack_offset
319 %undef stack_offset ; so that the current value of stack_offset doesn't get baked in by xdefine
bafad220
LM
320 %assign %%i 0
321 %rep %0
322 %xdefine %1q r %+ %%i %+ q
323 %xdefine %1d r %+ %%i %+ d
324 %xdefine %1w r %+ %%i %+ w
96c9cc10 325 %xdefine %1h r %+ %%i %+ h
bafad220 326 %xdefine %1b r %+ %%i %+ b
2f77923d 327 %xdefine %1m r %+ %%i %+ m
98b9da2a 328 %xdefine %1mp r %+ %%i %+ mp
bafad220
LM
329 CAT_XDEFINE arg_name, %%i, %1
330 %assign %%i %%i+1
331 %rotate 1
332 %endrep
0f53d0cf
LM
333 %xdefine stack_offset %%stack_offset
334 %assign n_arg_names %0
bafad220
LM
335%endmacro
336
9f1245eb
HG
337%define required_stack_alignment ((mmsize + 15) & ~15)
338
6f40e9f0
RB
339%macro ALLOC_STACK 1-2 0 ; stack_size, n_xmm_regs (for win64 only)
340 %ifnum %1
341 %if %1 != 0
9f1245eb 342 %assign %%pad 0
6f40e9f0
RB
343 %assign stack_size %1
344 %if stack_size < 0
345 %assign stack_size -stack_size
346 %endif
bbe4a6db 347 %if WIN64
9f1245eb 348 %assign %%pad %%pad + 32 ; shadow space
bbe4a6db
HG
349 %if mmsize != 8
350 %assign xmm_regs_used %2
351 %if xmm_regs_used > 8
9f1245eb 352 %assign %%pad %%pad + (xmm_regs_used-8)*16 ; callee-saved xmm registers
bbe4a6db
HG
353 %endif
354 %endif
a34d9ad9 355 %endif
9f1245eb
HG
356 %if required_stack_alignment <= STACK_ALIGNMENT
357 ; maintain the current stack alignment
358 %assign stack_size_padded stack_size + %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))
6f40e9f0
RB
359 SUB rsp, stack_size_padded
360 %else
a34d9ad9
RB
361 %assign %%reg_num (regs_used - 1)
362 %xdefine rstk r %+ %%reg_num
6f40e9f0
RB
363 ; align stack, and save original stack location directly above
364 ; it, i.e. in [rsp+stack_size_padded], so we can restore the
365 ; stack in a single instruction (i.e. mov rsp, rstk or mov
366 ; rsp, [rsp+stack_size_padded])
6f40e9f0 367 %if %1 < 0 ; need to store rsp on stack
9f1245eb
HG
368 %xdefine rstkm [rsp + stack_size + %%pad]
369 %assign %%pad %%pad + gprsize
6f40e9f0 370 %else ; can keep rsp in rstk during whole function
6f40e9f0
RB
371 %xdefine rstkm rstk
372 %endif
9f1245eb
HG
373 %assign stack_size_padded stack_size + ((%%pad + required_stack_alignment-1) & ~(required_stack_alignment-1))
374 mov rstk, rsp
375 and rsp, ~(required_stack_alignment-1)
376 sub rsp, stack_size_padded
377 movifnidn rstkm, rstk
6f40e9f0 378 %endif
bbe4a6db 379 WIN64_PUSH_XMM
6f40e9f0
RB
380 %endif
381 %endif
382%endmacro
383
384%macro SETUP_STACK_POINTER 1
385 %ifnum %1
9f1245eb 386 %if %1 != 0 && required_stack_alignment > STACK_ALIGNMENT
6f40e9f0
RB
387 %if %1 > 0
388 %assign regs_used (regs_used + 1)
91ed050f
HG
389 %endif
390 %if ARCH_X86_64 && regs_used < 5 + UNIX64 * 3
391 ; Ensure that we don't clobber any registers containing arguments. For UNIX64 we also preserve r6 (rax)
392 ; since it's used as a hidden argument in vararg functions to specify the number of vector registers used.
393 %assign regs_used 5 + UNIX64 * 3
6f40e9f0
RB
394 %endif
395 %endif
396 %endif
397%endmacro
398
399%macro DEFINE_ARGS_INTERNAL 3+
400 %ifnum %2
401 DEFINE_ARGS %3
402 %elif %1 == 4
403 DEFINE_ARGS %2
404 %elif %1 > 4
405 DEFINE_ARGS %2, %3
406 %endif
407%endmacro
408
3b15a6d7 409%if WIN64 ; Windows x64 ;=================================================
bafad220 410
96c9cc10
RB
411DECLARE_REG 0, rcx
412DECLARE_REG 1, rdx
413DECLARE_REG 2, R8
414DECLARE_REG 3, R9
415DECLARE_REG 4, R10, 40
416DECLARE_REG 5, R11, 48
417DECLARE_REG 6, rax, 56
418DECLARE_REG 7, rdi, 64
419DECLARE_REG 8, rsi, 72
420DECLARE_REG 9, rbx, 80
421DECLARE_REG 10, rbp, 88
422DECLARE_REG 11, R12, 96
423DECLARE_REG 12, R13, 104
424DECLARE_REG 13, R14, 112
425DECLARE_REG 14, R15, 120
3f87f39c 426
6f40e9f0 427%macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
729f90e2 428 %assign num_args %1
3f87f39c 429 %assign regs_used %2
729f90e2 430 ASSERT regs_used >= num_args
a34d9ad9 431 SETUP_STACK_POINTER %4
729f90e2
HG
432 ASSERT regs_used <= 15
433 PUSH_IF_USED 7, 8, 9, 10, 11, 12, 13, 14
6f40e9f0
RB
434 ALLOC_STACK %4, %3
435 %if mmsize != 8 && stack_size == 0
9cf73853
HG
436 WIN64_SPILL_XMM %3
437 %endif
729f90e2 438 LOAD_IF_USED 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
6f40e9f0
RB
439 DEFINE_ARGS_INTERNAL %0, %4, %5
440%endmacro
441
442%macro WIN64_PUSH_XMM 0
bbe4a6db
HG
443 ; Use the shadow space to store XMM6 and XMM7, the rest needs stack space allocated.
444 %if xmm_regs_used > 6
445 movaps [rstk + stack_offset + 8], xmm6
446 %endif
447 %if xmm_regs_used > 7
448 movaps [rstk + stack_offset + 24], xmm7
449 %endif
450 %if xmm_regs_used > 8
451 %assign %%i 8
452 %rep xmm_regs_used-8
453 movaps [rsp + (%%i-8)*16 + stack_size + 32], xmm %+ %%i
454 %assign %%i %%i+1
455 %endrep
456 %endif
532e7697
LM
457%endmacro
458
459%macro WIN64_SPILL_XMM 1
460 %assign xmm_regs_used %1
461 ASSERT xmm_regs_used <= 16
bbe4a6db 462 %if xmm_regs_used > 8
9f1245eb
HG
463 ; Allocate stack space for callee-saved xmm registers plus shadow space and align the stack.
464 %assign %%pad (xmm_regs_used-8)*16 + 32
465 %assign stack_size_padded %%pad + ((-%%pad-stack_offset-gprsize) & (STACK_ALIGNMENT-1))
bbe4a6db 466 SUB rsp, stack_size_padded
3f87f39c 467 %endif
bbe4a6db 468 WIN64_PUSH_XMM
3f87f39c
JA
469%endmacro
470
532e7697 471%macro WIN64_RESTORE_XMM_INTERNAL 1
bbe4a6db
HG
472 %assign %%pad_size 0
473 %if xmm_regs_used > 8
3f87f39c 474 %assign %%i xmm_regs_used
bbe4a6db 475 %rep xmm_regs_used-8
3f87f39c 476 %assign %%i %%i-1
bbe4a6db 477 movaps xmm %+ %%i, [%1 + (%%i-8)*16 + stack_size + 32]
3f87f39c 478 %endrep
6f40e9f0
RB
479 %endif
480 %if stack_size_padded > 0
9f1245eb 481 %if stack_size > 0 && required_stack_alignment > STACK_ALIGNMENT
6f40e9f0
RB
482 mov rsp, rstkm
483 %else
484 add %1, stack_size_padded
bbe4a6db 485 %assign %%pad_size stack_size_padded
6f40e9f0 486 %endif
3f87f39c 487 %endif
bbe4a6db
HG
488 %if xmm_regs_used > 7
489 movaps xmm7, [%1 + stack_offset - %%pad_size + 24]
490 %endif
491 %if xmm_regs_used > 6
492 movaps xmm6, [%1 + stack_offset - %%pad_size + 8]
493 %endif
3f87f39c
JA
494%endmacro
495
532e7697
LM
496%macro WIN64_RESTORE_XMM 1
497 WIN64_RESTORE_XMM_INTERNAL %1
6f40e9f0 498 %assign stack_offset (stack_offset-stack_size_padded)
3f87f39c
JA
499 %assign xmm_regs_used 0
500%endmacro
501
6f40e9f0 502%define has_epilogue regs_used > 7 || xmm_regs_used > 6 || mmsize == 32 || stack_size > 0
96c9cc10 503
3f87f39c 504%macro RET 0
532e7697 505 WIN64_RESTORE_XMM_INTERNAL rsp
729f90e2 506 POP_IF_USED 14, 13, 12, 11, 10, 9, 8, 7
30b45d9c
RB
507%if mmsize == 32
508 vzeroupper
509%endif
25cb0c1a 510 AUTO_REP_RET
bafad220
LM
511%endmacro
512
3b15a6d7 513%elif ARCH_X86_64 ; *nix x64 ;=============================================
bafad220 514
96c9cc10
RB
515DECLARE_REG 0, rdi
516DECLARE_REG 1, rsi
517DECLARE_REG 2, rdx
518DECLARE_REG 3, rcx
519DECLARE_REG 4, R8
520DECLARE_REG 5, R9
521DECLARE_REG 6, rax, 8
522DECLARE_REG 7, R10, 16
523DECLARE_REG 8, R11, 24
524DECLARE_REG 9, rbx, 32
525DECLARE_REG 10, rbp, 40
526DECLARE_REG 11, R12, 48
527DECLARE_REG 12, R13, 56
528DECLARE_REG 13, R14, 64
529DECLARE_REG 14, R15, 72
bafad220 530
6f40e9f0 531%macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
729f90e2
HG
532 %assign num_args %1
533 %assign regs_used %2
534 ASSERT regs_used >= num_args
a34d9ad9 535 SETUP_STACK_POINTER %4
729f90e2
HG
536 ASSERT regs_used <= 15
537 PUSH_IF_USED 9, 10, 11, 12, 13, 14
6f40e9f0 538 ALLOC_STACK %4
729f90e2 539 LOAD_IF_USED 6, 7, 8, 9, 10, 11, 12, 13, 14
6f40e9f0 540 DEFINE_ARGS_INTERNAL %0, %4, %5
bafad220
LM
541%endmacro
542
6f40e9f0 543%define has_epilogue regs_used > 9 || mmsize == 32 || stack_size > 0
96c9cc10 544
bafad220 545%macro RET 0
6f40e9f0 546%if stack_size_padded > 0
9f1245eb 547%if required_stack_alignment > STACK_ALIGNMENT
6f40e9f0
RB
548 mov rsp, rstkm
549%else
550 add rsp, stack_size_padded
551%endif
552%endif
729f90e2 553 POP_IF_USED 14, 13, 12, 11, 10, 9
30b45d9c
RB
554%if mmsize == 32
555 vzeroupper
556%endif
25cb0c1a 557 AUTO_REP_RET
bafad220
LM
558%endmacro
559
bafad220
LM
560%else ; X86_32 ;==============================================================
561
96c9cc10
RB
562DECLARE_REG 0, eax, 4
563DECLARE_REG 1, ecx, 8
564DECLARE_REG 2, edx, 12
565DECLARE_REG 3, ebx, 16
566DECLARE_REG 4, esi, 20
567DECLARE_REG 5, edi, 24
568DECLARE_REG 6, ebp, 28
bafad220
LM
569%define rsp esp
570
729f90e2
HG
571%macro DECLARE_ARG 1-*
572 %rep %0
6f40e9f0 573 %define r%1m [rstk + stack_offset + 4*%1 + 4]
729f90e2
HG
574 %define r%1mp dword r%1m
575 %rotate 1
576 %endrep
bafad220
LM
577%endmacro
578
729f90e2 579DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
bafad220 580
6f40e9f0 581%macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
729f90e2 582 %assign num_args %1
bafad220 583 %assign regs_used %2
a34d9ad9
RB
584 ASSERT regs_used >= num_args
585 %if num_args > 7
586 %assign num_args 7
587 %endif
729f90e2
HG
588 %if regs_used > 7
589 %assign regs_used 7
590 %endif
6f40e9f0
RB
591 SETUP_STACK_POINTER %4
592 ASSERT regs_used <= 7
729f90e2 593 PUSH_IF_USED 3, 4, 5, 6
6f40e9f0 594 ALLOC_STACK %4
729f90e2 595 LOAD_IF_USED 0, 1, 2, 3, 4, 5, 6
6f40e9f0 596 DEFINE_ARGS_INTERNAL %0, %4, %5
bafad220
LM
597%endmacro
598
6f40e9f0 599%define has_epilogue regs_used > 3 || mmsize == 32 || stack_size > 0
96c9cc10 600
bafad220 601%macro RET 0
6f40e9f0 602%if stack_size_padded > 0
9f1245eb 603%if required_stack_alignment > STACK_ALIGNMENT
6f40e9f0
RB
604 mov rsp, rstkm
605%else
606 add rsp, stack_size_padded
607%endif
608%endif
729f90e2 609 POP_IF_USED 6, 5, 4, 3
30b45d9c
RB
610%if mmsize == 32
611 vzeroupper
612%endif
25cb0c1a 613 AUTO_REP_RET
bafad220
LM
614%endmacro
615
bafad220
LM
616%endif ;======================================================================
617
3b15a6d7 618%if WIN64 == 0
532e7697
LM
619%macro WIN64_SPILL_XMM 1
620%endmacro
621%macro WIN64_RESTORE_XMM 1
622%endmacro
6f40e9f0
RB
623%macro WIN64_PUSH_XMM 0
624%endmacro
532e7697
LM
625%endif
626
25cb0c1a
LM
627; On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either
628; a branch or a branch target. So switch to a 2-byte form of ret in that case.
629; We can automatically detect "follows a branch", but not a branch target.
630; (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.)
96c9cc10
RB
631%macro REP_RET 0
632 %if has_epilogue
633 RET
634 %else
635 rep ret
636 %endif
637%endmacro
638
25cb0c1a
LM
639%define last_branch_adr $$
640%macro AUTO_REP_RET 0
641 %ifndef cpuflags
642 times ((last_branch_adr-$)>>31)+1 rep ; times 1 iff $ != last_branch_adr.
643 %elif notcpuflag(ssse3)
644 times ((last_branch_adr-$)>>31)+1 rep
645 %endif
646 ret
647%endmacro
648
649%macro BRANCH_INSTR 0-*
650 %rep %0
651 %macro %1 1-2 %1
652 %2 %1
653 %%branch_instr:
654 %xdefine last_branch_adr %%branch_instr
655 %endmacro
656 %rotate 1
657 %endrep
658%endmacro
659
660BRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae, jna, jnae, jb, jbe, jnb, jnbe, jc, jnc, js, jns, jo, jno, jp, jnp
661
96c9cc10
RB
662%macro TAIL_CALL 2 ; callee, is_nonadjacent
663 %if has_epilogue
664 call %1
665 RET
666 %elif %2
667 jmp %1
668 %endif
669%endmacro
670
bafad220
LM
671;=============================================================================
672; arch-independent part
673;=============================================================================
674
675%assign function_align 16
676
2f7f2e4b
LM
677; Begin a function.
678; Applies any symbol mangling needed for C linkage, and sets up a define such that
679; subsequent uses of the function name automatically refer to the mangled version.
680; Appends cpuflags to the function name if cpuflags has been specified.
d633d12b
DB
681; The "" empty default parameter is a workaround for nasm, which fails if SUFFIX
682; is empty and we call cglobal_internal with just %1 %+ SUFFIX (without %2).
a34d9ad9 683%macro cglobal 1-2+ "" ; name, [PROLOGUE args]
d633d12b
DB
684 cglobal_internal 1, %1 %+ SUFFIX, %2
685%endmacro
686%macro cvisible 1-2+ "" ; name, [PROLOGUE args]
687 cglobal_internal 0, %1 %+ SUFFIX, %2
688%endmacro
689%macro cglobal_internal 2-3+
690 %if %1
691 %xdefine %%FUNCTION_PREFIX private_prefix
692 %xdefine %%VISIBILITY hidden
693 %else
694 %xdefine %%FUNCTION_PREFIX public_prefix
695 %xdefine %%VISIBILITY
696 %endif
697 %ifndef cglobaled_%2
698 %xdefine %2 mangle(%%FUNCTION_PREFIX %+ _ %+ %2)
699 %xdefine %2.skip_prologue %2 %+ .skip_prologue
700 CAT_XDEFINE cglobaled_, %2, 1
2f7f2e4b 701 %endif
d633d12b 702 %xdefine current_function %2
44b44441 703 %if FORMAT_ELF
d633d12b 704 global %2:function %%VISIBILITY
bafad220 705 %else
d633d12b 706 global %2
bafad220
LM
707 %endif
708 align function_align
d633d12b 709 %2:
bbe4a6db
HG
710 RESET_MM_PERMUTATION ; needed for x86-64, also makes disassembly somewhat nicer
711 %xdefine rstk rsp ; copy of the original stack pointer, used when greater alignment than the known stack alignment is required
712 %assign stack_offset 0 ; stack pointer offset relative to the return address
713 %assign stack_size 0 ; amount of stack space that can be freely used inside a function
714 %assign stack_size_padded 0 ; total amount of allocated stack space, including space for callee-saved xmm registers on WIN64 and alignment padding
715 %assign xmm_regs_used 0 ; number of XMM registers requested, used for dealing with callee-saved registers on WIN64
d633d12b
DB
716 %ifnidn %3, ""
717 PROLOGUE %3
bafad220
LM
718 %endif
719%endmacro
720
721%macro cextern 1
ef5d41a5 722 %xdefine %1 mangle(private_prefix %+ _ %+ %1)
2f7f2e4b 723 CAT_XDEFINE cglobaled_, %1, 1
2966cc18
JGG
724 extern %1
725%endmacro
726
2f7f2e4b 727; like cextern, but without the prefix
2966cc18 728%macro cextern_naked 1
44b44441
HG
729 %ifdef PREFIX
730 %xdefine %1 mangle(%1)
731 %endif
2f7f2e4b 732 CAT_XDEFINE cglobaled_, %1, 1
3f87f39c 733 extern %1
bafad220
LM
734%endmacro
735
71155665 736%macro const 1-2+
ef5d41a5 737 %xdefine %1 mangle(private_prefix %+ _ %+ %1)
44b44441 738 %if FORMAT_ELF
ad76e6e7
HG
739 global %1:data hidden
740 %else
741 global %1
742 %endif
2966cc18
JGG
743 %1: %2
744%endmacro
745
44b44441
HG
746; This is needed for ELF, otherwise the GNU linker assumes the stack is executable by default.
747%if FORMAT_ELF
748 [SECTION .note.GNU-stack noalloc noexec nowrite progbits]
bafad220
LM
749%endif
750
2f7f2e4b
LM
751; cpuflags
752
753%assign cpuflags_mmx (1<<0)
754%assign cpuflags_mmx2 (1<<1) | cpuflags_mmx
755%assign cpuflags_3dnow (1<<2) | cpuflags_mmx
ca844b7b 756%assign cpuflags_3dnowext (1<<3) | cpuflags_3dnow
2f7f2e4b
LM
757%assign cpuflags_sse (1<<4) | cpuflags_mmx2
758%assign cpuflags_sse2 (1<<5) | cpuflags_sse
759%assign cpuflags_sse2slow (1<<6) | cpuflags_sse2
760%assign cpuflags_sse3 (1<<7) | cpuflags_sse2
761%assign cpuflags_ssse3 (1<<8) | cpuflags_sse3
762%assign cpuflags_sse4 (1<<9) | cpuflags_ssse3
763%assign cpuflags_sse42 (1<<10)| cpuflags_sse4
764%assign cpuflags_avx (1<<11)| cpuflags_sse42
765%assign cpuflags_xop (1<<12)| cpuflags_avx
766%assign cpuflags_fma4 (1<<13)| cpuflags_avx
44b44441
HG
767%assign cpuflags_fma3 (1<<14)| cpuflags_avx
768%assign cpuflags_avx2 (1<<15)| cpuflags_fma3
2f7f2e4b
LM
769
770%assign cpuflags_cache32 (1<<16)
771%assign cpuflags_cache64 (1<<17)
772%assign cpuflags_slowctz (1<<18)
773%assign cpuflags_lzcnt (1<<19)
3e2fa991
HG
774%assign cpuflags_aligned (1<<20) ; not a cpu feature, but a function variant
775%assign cpuflags_atom (1<<21)
776%assign cpuflags_bmi1 (1<<22)|cpuflags_lzcnt
777%assign cpuflags_bmi2 (1<<23)|cpuflags_bmi1
2f7f2e4b 778
7adcd4e8
HG
779; Returns a boolean value expressing whether or not the specified cpuflag is enabled.
780%define cpuflag(x) (((((cpuflags & (cpuflags_ %+ x)) ^ (cpuflags_ %+ x)) - 1) >> 31) & 1)
781%define notcpuflag(x) (cpuflag(x) ^ 1)
2f7f2e4b 782
f629705b 783; Takes an arbitrary number of cpuflags from the above list.
2f7f2e4b
LM
784; All subsequent functions (up to the next INIT_CPUFLAGS) is built for the specified cpu.
785; You shouldn't need to invoke this macro directly, it's a subroutine for INIT_MMX &co.
f629705b
HG
786%macro INIT_CPUFLAGS 0-*
787 %xdefine SUFFIX
788 %undef cpuname
789 %assign cpuflags 0
790
2f7f2e4b 791 %if %0 >= 1
f629705b
HG
792 %rep %0
793 %ifdef cpuname
794 %xdefine cpuname cpuname %+ _%1
795 %else
796 %xdefine cpuname %1
797 %endif
798 %assign cpuflags cpuflags | cpuflags_%1
799 %rotate 1
800 %endrep
2f7f2e4b 801 %xdefine SUFFIX _ %+ cpuname
f629705b 802
2f7f2e4b
LM
803 %if cpuflag(avx)
804 %assign avx_enabled 1
805 %endif
c108ba01 806 %if (mmsize == 16 && notcpuflag(sse2)) || (mmsize == 32 && notcpuflag(avx2))
f2bd8a07
JR
807 %define mova movaps
808 %define movu movups
809 %define movnta movntps
810 %endif
2f7f2e4b
LM
811 %if cpuflag(aligned)
812 %define movu mova
f629705b 813 %elif cpuflag(sse3) && notcpuflag(ssse3)
2f7f2e4b
LM
814 %define movu lddqu
815 %endif
f629705b
HG
816 %endif
817
44b44441 818 %if ARCH_X86_64 || cpuflag(sse2)
f629705b 819 CPUNOP amdnop
2f7f2e4b 820 %else
f629705b 821 CPUNOP basicnop
2f7f2e4b
LM
822 %endif
823%endmacro
824
3fb78e99 825; Merge mmx and sse*
176a0fca
HG
826; m# is a simd register of the currently selected size
827; xm# is the corresponding xmm register if mmsize >= 16, otherwise the same as m#
828; ym# is the corresponding ymm register if mmsize >= 32, otherwise the same as m#
3fb78e99 829; (All 3 remain in sync through SWAP.)
bafad220
LM
830
831%macro CAT_XDEFINE 3
832 %xdefine %1%2 %3
833%endmacro
834
835%macro CAT_UNDEF 2
836 %undef %1%2
837%endmacro
838
2f7f2e4b 839%macro INIT_MMX 0-1+
33cbfa6f 840 %assign avx_enabled 0
2f7f2e4b 841 %define RESET_MM_PERMUTATION INIT_MMX %1
bafad220
LM
842 %define mmsize 8
843 %define num_mmregs 8
844 %define mova movq
845 %define movu movq
846 %define movh movd
532e7697 847 %define movnta movntq
bafad220
LM
848 %assign %%i 0
849 %rep 8
850 CAT_XDEFINE m, %%i, mm %+ %%i
ec217218 851 CAT_XDEFINE nnmm, %%i, %%i
bafad220
LM
852 %assign %%i %%i+1
853 %endrep
854 %rep 8
855 CAT_UNDEF m, %%i
ec217218 856 CAT_UNDEF nnmm, %%i
bafad220
LM
857 %assign %%i %%i+1
858 %endrep
2f7f2e4b 859 INIT_CPUFLAGS %1
bafad220
LM
860%endmacro
861
2f7f2e4b 862%macro INIT_XMM 0-1+
33cbfa6f 863 %assign avx_enabled 0
2f7f2e4b 864 %define RESET_MM_PERMUTATION INIT_XMM %1
bafad220
LM
865 %define mmsize 16
866 %define num_mmregs 8
3b15a6d7 867 %if ARCH_X86_64
bafad220
LM
868 %define num_mmregs 16
869 %endif
870 %define mova movdqa
871 %define movu movdqu
872 %define movh movq
532e7697 873 %define movnta movntdq
bafad220
LM
874 %assign %%i 0
875 %rep num_mmregs
876 CAT_XDEFINE m, %%i, xmm %+ %%i
ec217218 877 CAT_XDEFINE nnxmm, %%i, %%i
bafad220
LM
878 %assign %%i %%i+1
879 %endrep
2f7f2e4b 880 INIT_CPUFLAGS %1
bafad220
LM
881%endmacro
882
2f7f2e4b 883%macro INIT_YMM 0-1+
33cbfa6f 884 %assign avx_enabled 1
2f7f2e4b 885 %define RESET_MM_PERMUTATION INIT_YMM %1
33cbfa6f
VS
886 %define mmsize 32
887 %define num_mmregs 8
3b15a6d7 888 %if ARCH_X86_64
33cbfa6f
VS
889 %define num_mmregs 16
890 %endif
c108ba01
HG
891 %define mova movdqa
892 %define movu movdqu
2f7f2e4b 893 %undef movh
c108ba01 894 %define movnta movntdq
33cbfa6f
VS
895 %assign %%i 0
896 %rep num_mmregs
897 CAT_XDEFINE m, %%i, ymm %+ %%i
f5e486f6 898 CAT_XDEFINE nnymm, %%i, %%i
33cbfa6f
VS
899 %assign %%i %%i+1
900 %endrep
2f7f2e4b 901 INIT_CPUFLAGS %1
33cbfa6f
VS
902%endmacro
903
2f7f2e4b 904INIT_XMM
bafad220 905
3fb78e99
LM
906%macro DECLARE_MMCAST 1
907 %define mmmm%1 mm%1
908 %define mmxmm%1 mm%1
909 %define mmymm%1 mm%1
910 %define xmmmm%1 mm%1
911 %define xmmxmm%1 xmm%1
912 %define xmmymm%1 xmm%1
913 %define ymmmm%1 mm%1
176a0fca 914 %define ymmxmm%1 xmm%1
3fb78e99
LM
915 %define ymmymm%1 ymm%1
916 %define xm%1 xmm %+ m%1
917 %define ym%1 ymm %+ m%1
918%endmacro
919
920%assign i 0
921%rep 16
922 DECLARE_MMCAST i
923%assign i i+1
924%endrep
925
bafad220
LM
926; I often want to use macros that permute their arguments. e.g. there's no
927; efficient way to implement butterfly or transpose or dct without swapping some
928; arguments.
929;
930; I would like to not have to manually keep track of the permutations:
931; If I insert a permutation in the middle of a function, it should automatically
932; change everything that follows. For more complex macros I may also have multiple
933; implementations, e.g. the SSE2 and SSSE3 versions may have different permutations.
934;
935; Hence these macros. Insert a PERMUTE or some SWAPs at the end of a macro that
936; permutes its arguments. It's equivalent to exchanging the contents of the
937; registers, except that this way you exchange the register names instead, so it
938; doesn't cost any cycles.
939
940%macro PERMUTE 2-* ; takes a list of pairs to swap
941%rep %0/2
49ebe3f9 942 %xdefine %%tmp%2 m%2
bafad220
LM
943 %rotate 2
944%endrep
945%rep %0/2
49ebe3f9 946 %xdefine m%1 %%tmp%2
ec217218 947 CAT_XDEFINE nn, m%1, %1
bafad220
LM
948 %rotate 2
949%endrep
950%endmacro
951
49ebe3f9
LM
952%macro SWAP 2+ ; swaps a single chain (sometimes more concise than pairs)
953%ifnum %1 ; SWAP 0, 1, ...
954 SWAP_INTERNAL_NUM %1, %2
955%else ; SWAP m0, m1, ...
956 SWAP_INTERNAL_NAME %1, %2
bafad220 957%endif
49ebe3f9
LM
958%endmacro
959
960%macro SWAP_INTERNAL_NUM 2-*
961 %rep %0-1
962 %xdefine %%tmp m%1
963 %xdefine m%1 m%2
964 %xdefine m%2 %%tmp
ec217218
LM
965 CAT_XDEFINE nn, m%1, %1
966 CAT_XDEFINE nn, m%2, %2
bafad220 967 %rotate 1
49ebe3f9
LM
968 %endrep
969%endmacro
970
971%macro SWAP_INTERNAL_NAME 2-*
ec217218 972 %xdefine %%args nn %+ %1
49ebe3f9 973 %rep %0-1
ec217218 974 %xdefine %%args %%args, nn %+ %2
49ebe3f9
LM
975 %rotate 1
976 %endrep
977 SWAP_INTERNAL_NUM %%args
bafad220
LM
978%endmacro
979
2f7f2e4b
LM
980; If SAVE_MM_PERMUTATION is placed at the end of a function, then any later
981; calls to that function will automatically load the permutation, so values can
982; be returned in mmregs.
983%macro SAVE_MM_PERMUTATION 0-1
984 %if %0
985 %xdefine %%f %1_m
986 %else
987 %xdefine %%f current_function %+ _m
988 %endif
bafad220
LM
989 %assign %%i 0
990 %rep num_mmregs
2f7f2e4b 991 CAT_XDEFINE %%f, %%i, m %+ %%i
bafad220
LM
992 %assign %%i %%i+1
993 %endrep
994%endmacro
995
2966cc18 996%macro LOAD_MM_PERMUTATION 1 ; name to load from
2f7f2e4b
LM
997 %ifdef %1_m0
998 %assign %%i 0
999 %rep num_mmregs
1000 CAT_XDEFINE m, %%i, %1_m %+ %%i
ec217218 1001 CAT_XDEFINE nn, m %+ %%i, %%i
2f7f2e4b
LM
1002 %assign %%i %%i+1
1003 %endrep
1004 %endif
bafad220
LM
1005%endmacro
1006
2f7f2e4b 1007; Append cpuflags to the callee's name iff the appended name is known and the plain name isn't
bafad220 1008%macro call 1
edd82267 1009 call_internal %1 %+ SUFFIX, %1
2f7f2e4b
LM
1010%endmacro
1011%macro call_internal 2
edd82267
MR
1012 %xdefine %%i %2
1013 %ifndef cglobaled_%2
1014 %ifdef cglobaled_%1
1015 %xdefine %%i %1
2f7f2e4b 1016 %endif
bafad220 1017 %endif
2f7f2e4b
LM
1018 call %%i
1019 LOAD_MM_PERMUTATION %%i
bafad220
LM
1020%endmacro
1021
2966cc18 1022; Substitutions that reduce instruction size but are functionally equivalent
3f87f39c
JA
1023%macro add 2
1024 %ifnum %2
1025 %if %2==128
1026 sub %1, -128
1027 %else
1028 add %1, %2
1029 %endif
1030 %else
1031 add %1, %2
1032 %endif
1033%endmacro
1034
1035%macro sub 2
1036 %ifnum %2
1037 %if %2==128
1038 add %1, -128
1039 %else
1040 sub %1, %2
1041 %endif
1042 %else
1043 sub %1, %2
1044 %endif
1045%endmacro
33cbfa6f
VS
1046
1047;=============================================================================
1048; AVX abstraction layer
1049;=============================================================================
1050
1051%assign i 0
1052%rep 16
1053 %if i < 8
1054 CAT_XDEFINE sizeofmm, i, 8
1055 %endif
1056 CAT_XDEFINE sizeofxmm, i, 16
1057 CAT_XDEFINE sizeofymm, i, 32
1058%assign i i+1
1059%endrep
1060%undef i
1061
96c9cc10
RB
1062%macro CHECK_AVX_INSTR_EMU 3-*
1063 %xdefine %%opcode %1
1064 %xdefine %%dst %2
1065 %rep %0-2
1066 %ifidn %%dst, %3
1067 %error non-avx emulation of ``%%opcode'' is not supported
1068 %endif
1069 %rotate 1
1070 %endrep
1071%endmacro
1072
33cbfa6f 1073;%1 == instruction
b114d28a
AM
1074;%2 == minimal instruction set
1075;%3 == 1 if float, 0 if int
1076;%4 == 1 if non-destructive or 4-operand (xmm, xmm, xmm, imm), 0 otherwise
1077;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
1078;%6+: operands
1079%macro RUN_AVX_INSTR 6-9+
1080 %ifnum sizeof%7
1081 %assign __sizeofreg sizeof%7
1082 %elifnum sizeof%6
b7d0d10a 1083 %assign __sizeofreg sizeof%6
2f7f2e4b 1084 %else
b7d0d10a 1085 %assign __sizeofreg mmsize
2f7f2e4b 1086 %endif
b7d0d10a
LM
1087 %assign __emulate_avx 0
1088 %if avx_enabled && __sizeofreg >= 16
1089 %xdefine __instr v%1
33cbfa6f 1090 %else
b7d0d10a 1091 %xdefine __instr %1
b114d28a 1092 %if %0 >= 8+%4
b7d0d10a 1093 %assign __emulate_avx 1
33cbfa6f 1094 %endif
c108ba01 1095 %endif
b114d28a
AM
1096 %ifnidn %2, fnord
1097 %ifdef cpuname
1098 %if notcpuflag(%2)
1099 %error use of ``%1'' %2 instruction in cpuname function: current_function
1100 %elif cpuflags_%2 < cpuflags_sse && notcpuflag(sse2) && __sizeofreg > 8
1101 %error use of ``%1'' sse2 instruction in cpuname function: current_function
1102 %endif
1103 %endif
1104 %endif
33cbfa6f 1105
b7d0d10a 1106 %if __emulate_avx
b114d28a
AM
1107 %xdefine __src1 %7
1108 %xdefine __src2 %8
1109 %ifnidn %6, %7
1110 %if %0 >= 9
1111 CHECK_AVX_INSTR_EMU {%1 %6, %7, %8, %9}, %6, %8, %9
c108ba01 1112 %else
b114d28a 1113 CHECK_AVX_INSTR_EMU {%1 %6, %7, %8}, %6, %8
c108ba01 1114 %endif
b114d28a
AM
1115 %if %5 && %4 == 0
1116 %ifnid %8
c108ba01
HG
1117 ; 3-operand AVX instructions with a memory arg can only have it in src2,
1118 ; whereas SSE emulation prefers to have it in src1 (i.e. the mov).
1119 ; So, if the instruction is commutative with a memory arg, swap them.
b114d28a
AM
1120 %xdefine __src1 %8
1121 %xdefine __src2 %7
33cbfa6f 1122 %endif
c108ba01 1123 %endif
b7d0d10a 1124 %if __sizeofreg == 8
b114d28a
AM
1125 MOVQ %6, __src1
1126 %elif %3
1127 MOVAPS %6, __src1
33cbfa6f 1128 %else
b114d28a 1129 MOVDQA %6, __src1
33cbfa6f 1130 %endif
33cbfa6f 1131 %endif
b114d28a
AM
1132 %if %0 >= 9
1133 %1 %6, __src2, %9
c108ba01 1134 %else
b114d28a 1135 %1 %6, __src2
2f7f2e4b 1136 %endif
b114d28a
AM
1137 %elif %0 >= 9
1138 __instr %6, %7, %8, %9
1139 %elif %0 == 8
1140 __instr %6, %7, %8
c108ba01 1141 %elif %0 == 7
b114d28a 1142 __instr %6, %7
2f7f2e4b 1143 %else
b114d28a 1144 __instr %6
2f7f2e4b
LM
1145 %endif
1146%endmacro
1147
33cbfa6f 1148;%1 == instruction
b114d28a
AM
1149;%2 == minimal instruction set
1150;%3 == 1 if float, 0 if int
1151;%4 == 1 if non-destructive or 4-operand (xmm, xmm, xmm, imm), 0 otherwise
1152;%5 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
1153%macro AVX_INSTR 1-5 fnord, 0, 1, 0
1154 %macro %1 1-10 fnord, fnord, fnord, fnord, %1, %2, %3, %4, %5
c108ba01 1155 %ifidn %2, fnord
b114d28a 1156 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1
c108ba01 1157 %elifidn %3, fnord
b114d28a 1158 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2
33cbfa6f 1159 %elifidn %4, fnord
b114d28a 1160 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3
33cbfa6f 1161 %elifidn %5, fnord
b114d28a 1162 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4
33cbfa6f 1163 %else
b114d28a 1164 RUN_AVX_INSTR %6, %7, %8, %9, %10, %1, %2, %3, %4, %5
33cbfa6f
VS
1165 %endif
1166 %endmacro
1167%endmacro
1168
c108ba01
HG
1169; Instructions with both VEX and non-VEX encodings
1170; Non-destructive instructions are written without parameters
b114d28a
AM
1171AVX_INSTR addpd, sse2, 1, 0, 1
1172AVX_INSTR addps, sse, 1, 0, 1
1173AVX_INSTR addsd, sse2, 1, 0, 1
1174AVX_INSTR addss, sse, 1, 0, 1
1175AVX_INSTR addsubpd, sse3, 1, 0, 0
1176AVX_INSTR addsubps, sse3, 1, 0, 0
1177AVX_INSTR aesdec, fnord, 0, 0, 0
1178AVX_INSTR aesdeclast, fnord, 0, 0, 0
1179AVX_INSTR aesenc, fnord, 0, 0, 0
1180AVX_INSTR aesenclast, fnord, 0, 0, 0
c108ba01
HG
1181AVX_INSTR aesimc
1182AVX_INSTR aeskeygenassist
b114d28a
AM
1183AVX_INSTR andnpd, sse2, 1, 0, 0
1184AVX_INSTR andnps, sse, 1, 0, 0
1185AVX_INSTR andpd, sse2, 1, 0, 1
1186AVX_INSTR andps, sse, 1, 0, 1
1187AVX_INSTR blendpd, sse4, 1, 0, 0
1188AVX_INSTR blendps, sse4, 1, 0, 0
1189AVX_INSTR blendvpd, sse4, 1, 0, 0
1190AVX_INSTR blendvps, sse4, 1, 0, 0
1191AVX_INSTR cmppd, sse2, 1, 1, 0
1192AVX_INSTR cmpps, sse, 1, 1, 0
1193AVX_INSTR cmpsd, sse2, 1, 1, 0
1194AVX_INSTR cmpss, sse, 1, 1, 0
1195AVX_INSTR comisd, sse2
1196AVX_INSTR comiss, sse
1197AVX_INSTR cvtdq2pd, sse2
1198AVX_INSTR cvtdq2ps, sse2
1199AVX_INSTR cvtpd2dq, sse2
1200AVX_INSTR cvtpd2ps, sse2
1201AVX_INSTR cvtps2dq, sse2
1202AVX_INSTR cvtps2pd, sse2
1203AVX_INSTR cvtsd2si, sse2
1204AVX_INSTR cvtsd2ss, sse2
1205AVX_INSTR cvtsi2sd, sse2
1206AVX_INSTR cvtsi2ss, sse
1207AVX_INSTR cvtss2sd, sse2
1208AVX_INSTR cvtss2si, sse
1209AVX_INSTR cvttpd2dq, sse2
1210AVX_INSTR cvttps2dq, sse2
1211AVX_INSTR cvttsd2si, sse2
1212AVX_INSTR cvttss2si, sse
1213AVX_INSTR divpd, sse2, 1, 0, 0
1214AVX_INSTR divps, sse, 1, 0, 0
1215AVX_INSTR divsd, sse2, 1, 0, 0
1216AVX_INSTR divss, sse, 1, 0, 0
1217AVX_INSTR dppd, sse4, 1, 1, 0
1218AVX_INSTR dpps, sse4, 1, 1, 0
1219AVX_INSTR extractps, sse4
1220AVX_INSTR haddpd, sse3, 1, 0, 0
1221AVX_INSTR haddps, sse3, 1, 0, 0
1222AVX_INSTR hsubpd, sse3, 1, 0, 0
1223AVX_INSTR hsubps, sse3, 1, 0, 0
1224AVX_INSTR insertps, sse4, 1, 1, 0
1225AVX_INSTR lddqu, sse3
1226AVX_INSTR ldmxcsr, sse
1227AVX_INSTR maskmovdqu, sse2
1228AVX_INSTR maxpd, sse2, 1, 0, 1
1229AVX_INSTR maxps, sse, 1, 0, 1
1230AVX_INSTR maxsd, sse2, 1, 0, 1
1231AVX_INSTR maxss, sse, 1, 0, 1
1232AVX_INSTR minpd, sse2, 1, 0, 1
1233AVX_INSTR minps, sse, 1, 0, 1
1234AVX_INSTR minsd, sse2, 1, 0, 1
1235AVX_INSTR minss, sse, 1, 0, 1
1236AVX_INSTR movapd, sse2
1237AVX_INSTR movaps, sse
1238AVX_INSTR movd, mmx
1239AVX_INSTR movddup, sse3
1240AVX_INSTR movdqa, sse2
1241AVX_INSTR movdqu, sse2
1242AVX_INSTR movhlps, sse, 1, 0, 0
1243AVX_INSTR movhpd, sse2, 1, 0, 0
1244AVX_INSTR movhps, sse, 1, 0, 0
1245AVX_INSTR movlhps, sse, 1, 0, 0
1246AVX_INSTR movlpd, sse2, 1, 0, 0
1247AVX_INSTR movlps, sse, 1, 0, 0
1248AVX_INSTR movmskpd, sse2
1249AVX_INSTR movmskps, sse
1250AVX_INSTR movntdq, sse2
1251AVX_INSTR movntdqa, sse4
1252AVX_INSTR movntpd, sse2
1253AVX_INSTR movntps, sse
1254AVX_INSTR movq, mmx
1255AVX_INSTR movsd, sse2, 1, 0, 0
1256AVX_INSTR movshdup, sse3
1257AVX_INSTR movsldup, sse3
1258AVX_INSTR movss, sse, 1, 0, 0
1259AVX_INSTR movupd, sse2
1260AVX_INSTR movups, sse
1261AVX_INSTR mpsadbw, sse4
1262AVX_INSTR mulpd, sse2, 1, 0, 1
1263AVX_INSTR mulps, sse, 1, 0, 1
1264AVX_INSTR mulsd, sse2, 1, 0, 1
1265AVX_INSTR mulss, sse, 1, 0, 1
1266AVX_INSTR orpd, sse2, 1, 0, 1
1267AVX_INSTR orps, sse, 1, 0, 1
1268AVX_INSTR pabsb, ssse3
1269AVX_INSTR pabsd, ssse3
1270AVX_INSTR pabsw, ssse3
1271AVX_INSTR packsswb, mmx, 0, 0, 0
1272AVX_INSTR packssdw, mmx, 0, 0, 0
1273AVX_INSTR packuswb, mmx, 0, 0, 0
1274AVX_INSTR packusdw, sse4, 0, 0, 0
1275AVX_INSTR paddb, mmx, 0, 0, 1
1276AVX_INSTR paddw, mmx, 0, 0, 1
1277AVX_INSTR paddd, mmx, 0, 0, 1
1278AVX_INSTR paddq, sse2, 0, 0, 1
1279AVX_INSTR paddsb, mmx, 0, 0, 1
1280AVX_INSTR paddsw, mmx, 0, 0, 1
1281AVX_INSTR paddusb, mmx, 0, 0, 1
1282AVX_INSTR paddusw, mmx, 0, 0, 1
1283AVX_INSTR palignr, ssse3
1284AVX_INSTR pand, mmx, 0, 0, 1
1285AVX_INSTR pandn, mmx, 0, 0, 0
1286AVX_INSTR pavgb, mmx2, 0, 0, 1
1287AVX_INSTR pavgw, mmx2, 0, 0, 1
1288AVX_INSTR pblendvb, sse4, 0, 0, 0
1289AVX_INSTR pblendw, sse4
1290AVX_INSTR pclmulqdq
1291AVX_INSTR pcmpestri, sse42
1292AVX_INSTR pcmpestrm, sse42
1293AVX_INSTR pcmpistri, sse42
1294AVX_INSTR pcmpistrm, sse42
1295AVX_INSTR pcmpeqb, mmx, 0, 0, 1
1296AVX_INSTR pcmpeqw, mmx, 0, 0, 1
1297AVX_INSTR pcmpeqd, mmx, 0, 0, 1
1298AVX_INSTR pcmpeqq, sse4, 0, 0, 1
1299AVX_INSTR pcmpgtb, mmx, 0, 0, 0
1300AVX_INSTR pcmpgtw, mmx, 0, 0, 0
1301AVX_INSTR pcmpgtd, mmx, 0, 0, 0
1302AVX_INSTR pcmpgtq, sse42, 0, 0, 0
1303AVX_INSTR pextrb, sse4
1304AVX_INSTR pextrd, sse4
1305AVX_INSTR pextrq, sse4
1306AVX_INSTR pextrw, mmx2
1307AVX_INSTR phaddw, ssse3, 0, 0, 0
1308AVX_INSTR phaddd, ssse3, 0, 0, 0
1309AVX_INSTR phaddsw, ssse3, 0, 0, 0
1310AVX_INSTR phminposuw, sse4
1311AVX_INSTR phsubw, ssse3, 0, 0, 0
1312AVX_INSTR phsubd, ssse3, 0, 0, 0
1313AVX_INSTR phsubsw, ssse3, 0, 0, 0
1314AVX_INSTR pinsrb, sse4
1315AVX_INSTR pinsrd, sse4
1316AVX_INSTR pinsrq, sse4
1317AVX_INSTR pinsrw, mmx2
1318AVX_INSTR pmaddwd, mmx, 0, 0, 1
1319AVX_INSTR pmaddubsw, ssse3, 0, 0, 0
1320AVX_INSTR pmaxsb, sse4, 0, 0, 1
1321AVX_INSTR pmaxsw, mmx2, 0, 0, 1
1322AVX_INSTR pmaxsd, sse4, 0, 0, 1
1323AVX_INSTR pmaxub, mmx2, 0, 0, 1
1324AVX_INSTR pmaxuw, sse4, 0, 0, 1
1325AVX_INSTR pmaxud, sse4, 0, 0, 1
1326AVX_INSTR pminsb, sse4, 0, 0, 1
1327AVX_INSTR pminsw, mmx2, 0, 0, 1
1328AVX_INSTR pminsd, sse4, 0, 0, 1
1329AVX_INSTR pminub, mmx2, 0, 0, 1
1330AVX_INSTR pminuw, sse4, 0, 0, 1
1331AVX_INSTR pminud, sse4, 0, 0, 1
1332AVX_INSTR pmovmskb, mmx2
1333AVX_INSTR pmovsxbw, sse4
1334AVX_INSTR pmovsxbd, sse4
1335AVX_INSTR pmovsxbq, sse4
1336AVX_INSTR pmovsxwd, sse4
1337AVX_INSTR pmovsxwq, sse4
1338AVX_INSTR pmovsxdq, sse4
1339AVX_INSTR pmovzxbw, sse4
1340AVX_INSTR pmovzxbd, sse4
1341AVX_INSTR pmovzxbq, sse4
1342AVX_INSTR pmovzxwd, sse4
1343AVX_INSTR pmovzxwq, sse4
1344AVX_INSTR pmovzxdq, sse4
1345AVX_INSTR pmuldq, sse4, 0, 0, 1
1346AVX_INSTR pmulhrsw, ssse3, 0, 0, 1
1347AVX_INSTR pmulhuw, mmx2, 0, 0, 1
1348AVX_INSTR pmulhw, mmx, 0, 0, 1
1349AVX_INSTR pmullw, mmx, 0, 0, 1
1350AVX_INSTR pmulld, sse4, 0, 0, 1
1351AVX_INSTR pmuludq, sse2, 0, 0, 1
1352AVX_INSTR por, mmx, 0, 0, 1
1353AVX_INSTR psadbw, mmx2, 0, 0, 1
1354AVX_INSTR pshufb, ssse3, 0, 0, 0
1355AVX_INSTR pshufd, sse2
1356AVX_INSTR pshufhw, sse2
1357AVX_INSTR pshuflw, sse2
1358AVX_INSTR psignb, ssse3, 0, 0, 0
1359AVX_INSTR psignw, ssse3, 0, 0, 0
1360AVX_INSTR psignd, ssse3, 0, 0, 0
1361AVX_INSTR psllw, mmx, 0, 0, 0
1362AVX_INSTR pslld, mmx, 0, 0, 0
1363AVX_INSTR psllq, mmx, 0, 0, 0
1364AVX_INSTR pslldq, sse2, 0, 0, 0
1365AVX_INSTR psraw, mmx, 0, 0, 0
1366AVX_INSTR psrad, mmx, 0, 0, 0
1367AVX_INSTR psrlw, mmx, 0, 0, 0
1368AVX_INSTR psrld, mmx, 0, 0, 0
1369AVX_INSTR psrlq, mmx, 0, 0, 0
1370AVX_INSTR psrldq, sse2, 0, 0, 0
1371AVX_INSTR psubb, mmx, 0, 0, 0
1372AVX_INSTR psubw, mmx, 0, 0, 0
1373AVX_INSTR psubd, mmx, 0, 0, 0
1374AVX_INSTR psubq, sse2, 0, 0, 0
1375AVX_INSTR psubsb, mmx, 0, 0, 0
1376AVX_INSTR psubsw, mmx, 0, 0, 0
1377AVX_INSTR psubusb, mmx, 0, 0, 0
1378AVX_INSTR psubusw, mmx, 0, 0, 0
1379AVX_INSTR ptest, sse4
1380AVX_INSTR punpckhbw, mmx, 0, 0, 0
1381AVX_INSTR punpckhwd, mmx, 0, 0, 0
1382AVX_INSTR punpckhdq, mmx, 0, 0, 0
1383AVX_INSTR punpckhqdq, sse2, 0, 0, 0
1384AVX_INSTR punpcklbw, mmx, 0, 0, 0
1385AVX_INSTR punpcklwd, mmx, 0, 0, 0
1386AVX_INSTR punpckldq, mmx, 0, 0, 0
1387AVX_INSTR punpcklqdq, sse2, 0, 0, 0
1388AVX_INSTR pxor, mmx, 0, 0, 1
1389AVX_INSTR rcpps, sse, 1, 0, 0
1390AVX_INSTR rcpss, sse, 1, 0, 0
1391AVX_INSTR roundpd, sse4
1392AVX_INSTR roundps, sse4
1393AVX_INSTR roundsd, sse4
1394AVX_INSTR roundss, sse4
1395AVX_INSTR rsqrtps, sse, 1, 0, 0
1396AVX_INSTR rsqrtss, sse, 1, 0, 0
1397AVX_INSTR shufpd, sse2, 1, 1, 0
1398AVX_INSTR shufps, sse, 1, 1, 0
1399AVX_INSTR sqrtpd, sse2, 1, 0, 0
1400AVX_INSTR sqrtps, sse, 1, 0, 0
1401AVX_INSTR sqrtsd, sse2, 1, 0, 0
1402AVX_INSTR sqrtss, sse, 1, 0, 0
1403AVX_INSTR stmxcsr, sse
1404AVX_INSTR subpd, sse2, 1, 0, 0
1405AVX_INSTR subps, sse, 1, 0, 0
1406AVX_INSTR subsd, sse2, 1, 0, 0
1407AVX_INSTR subss, sse, 1, 0, 0
1408AVX_INSTR ucomisd, sse2
1409AVX_INSTR ucomiss, sse
1410AVX_INSTR unpckhpd, sse2, 1, 0, 0
1411AVX_INSTR unpckhps, sse, 1, 0, 0
1412AVX_INSTR unpcklpd, sse2, 1, 0, 0
1413AVX_INSTR unpcklps, sse, 1, 0, 0
1414AVX_INSTR xorpd, sse2, 1, 0, 1
1415AVX_INSTR xorps, sse, 1, 0, 1
33cbfa6f
VS
1416
1417; 3DNow instructions, for sharing code between AVX, SSE and 3DN
b114d28a
AM
1418AVX_INSTR pfadd, 3dnow, 1, 0, 1
1419AVX_INSTR pfsub, 3dnow, 1, 0, 0
1420AVX_INSTR pfmul, 3dnow, 1, 0, 1
2f7f2e4b
LM
1421
1422; base-4 constants for shuffles
1423%assign i 0
1424%rep 256
1425 %assign j ((i>>6)&3)*1000 + ((i>>4)&3)*100 + ((i>>2)&3)*10 + (i&3)
1426 %if j < 10
1427 CAT_XDEFINE q000, j, i
1428 %elif j < 100
1429 CAT_XDEFINE q00, j, i
1430 %elif j < 1000
1431 CAT_XDEFINE q0, j, i
1432 %else
1433 CAT_XDEFINE q, j, i
1434 %endif
1435%assign i i+1
1436%endrep
1437%undef i
1438%undef j
1439
1440%macro FMA_INSTR 3
20689570
DB
1441 %macro %1 4-7 %1, %2, %3
1442 %if cpuflag(xop)
1443 v%5 %1, %2, %3, %4
8c75ba55 1444 %elifnidn %1, %4
20689570
DB
1445 %6 %1, %2, %3
1446 %7 %1, %4
8c75ba55
AM
1447 %else
1448 %error non-xop emulation of ``%5 %1, %2, %3, %4'' is not supported
2f7f2e4b
LM
1449 %endif
1450 %endmacro
1451%endmacro
1452
2f7f2e4b 1453FMA_INSTR pmacsww, pmullw, paddw
8c75ba55
AM
1454FMA_INSTR pmacsdd, pmulld, paddd ; sse4 emulation
1455FMA_INSTR pmacsdql, pmuldq, paddq ; sse4 emulation
2f7f2e4b 1456FMA_INSTR pmadcswd, pmaddwd, paddd
96c9cc10
RB
1457
1458; tzcnt is equivalent to "rep bsf" and is backwards-compatible with bsf.
1459; This lets us use tzcnt without bumping the yasm version requirement yet.
1460%define tzcnt rep bsf
c6908d6b 1461
715eb7ca
HG
1462; Macros for consolidating FMA3 and FMA4 using 4-operand (dst, src1, src2, src3) syntax.
1463; FMA3 is only possible if dst is the same as one of the src registers.
1464; Either src2 or src3 can be a memory operand.
1465%macro FMA4_INSTR 2-*
1466 %push fma4_instr
1467 %xdefine %$prefix %1
1468 %rep %0 - 1
1469 %macro %$prefix%2 4-6 %$prefix, %2
1470 %if notcpuflag(fma3) && notcpuflag(fma4)
1471 %error use of ``%5%6'' fma instruction in cpuname function: current_function
1472 %elif cpuflag(fma4)
1473 v%5%6 %1, %2, %3, %4
1474 %elifidn %1, %2
1475 ; If %3 or %4 is a memory operand it needs to be encoded as the last operand.
1476 %ifid %3
1477 v%{5}213%6 %2, %3, %4
1478 %else
1479 v%{5}132%6 %2, %4, %3
1480 %endif
1481 %elifidn %1, %3
1482 v%{5}213%6 %3, %2, %4
1483 %elifidn %1, %4
1484 v%{5}231%6 %4, %2, %3
1485 %else
1486 %error fma3 emulation of ``%5%6 %1, %2, %3, %4'' is not supported
1487 %endif
1488 %endmacro
1489 %rotate 1
1490 %endrep
1491 %pop
c6908d6b
JGG
1492%endmacro
1493
715eb7ca
HG
1494FMA4_INSTR fmadd, pd, ps, sd, ss
1495FMA4_INSTR fmaddsub, pd, ps
1496FMA4_INSTR fmsub, pd, ps, sd, ss
1497FMA4_INSTR fmsubadd, pd, ps
1498FMA4_INSTR fnmadd, pd, ps, sd, ss
1499FMA4_INSTR fnmsub, pd, ps, sd, ss
a3fabc6c 1500
1c6bb813
HG
1501; workaround: vpbroadcastq is broken in x86_32 due to a yasm bug (fixed in 1.3.0)
1502%ifdef __YASM_VER__
1503 %if __YASM_VERSION_ID__ < 0x01030000 && ARCH_X86_64 == 0
1504 %macro vpbroadcastq 2
1505 %if sizeof%1 == 16
1506 movddup %1, %2
1507 %else
1508 vbroadcastsd %1, %2
1509 %endif
1510 %endmacro
1511 %endif
a3fabc6c 1512%endif