Remove PPC perf counter support
[libav.git] / libavcodec / ppc / dsputil_ppc.c
1 /*
2 * Copyright (c) 2002 Brian Foley
3 * Copyright (c) 2002 Dieter Shirley
4 * Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org>
5 *
6 * This file is part of FFmpeg.
7 *
8 * FFmpeg is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * FFmpeg is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with FFmpeg; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23 #include "libavcodec/dsputil.h"
24 #include "dsputil_altivec.h"
25
26 int mm_flags = 0;
27
28 int mm_support(void)
29 {
30 int result = 0;
31 #if HAVE_ALTIVEC
32 if (has_altivec()) {
33 result |= FF_MM_ALTIVEC;
34 }
35 #endif /* result */
36 return result;
37 }
38
39 /* ***** WARNING ***** WARNING ***** WARNING ***** */
40 /*
41 clear_blocks_dcbz32_ppc will not work properly on PowerPC processors with a
42 cache line size not equal to 32 bytes.
43 Fortunately all processor used by Apple up to at least the 7450 (aka second
44 generation G4) use 32 bytes cache line.
45 This is due to the use of the 'dcbz' instruction. It simply clear to zero a
46 single cache line, so you need to know the cache line size to use it !
47 It's absurd, but it's fast...
48
49 update 24/06/2003 : Apple released yesterday the G5, with a PPC970. cache line
50 size: 128 bytes. Oups.
51 The semantic of dcbz was changed, it always clear 32 bytes. so the function
52 below will work, but will be slow. So I fixed check_dcbz_effect to use dcbzl,
53 which is defined to clear a cache line (as dcbz before). So we still can
54 distinguish, and use dcbz (32 bytes) or dcbzl (one cache line) as required.
55
56 see <http://developer.apple.com/technotes/tn/tn2087.html>
57 and <http://developer.apple.com/technotes/tn/tn2086.html>
58 */
59 static void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
60 {
61 register int misal = ((unsigned long)blocks & 0x00000010);
62 register int i = 0;
63 #if 1
64 if (misal) {
65 ((unsigned long*)blocks)[0] = 0L;
66 ((unsigned long*)blocks)[1] = 0L;
67 ((unsigned long*)blocks)[2] = 0L;
68 ((unsigned long*)blocks)[3] = 0L;
69 i += 16;
70 }
71 for ( ; i < sizeof(DCTELEM)*6*64-31 ; i += 32) {
72 __asm__ volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory");
73 }
74 if (misal) {
75 ((unsigned long*)blocks)[188] = 0L;
76 ((unsigned long*)blocks)[189] = 0L;
77 ((unsigned long*)blocks)[190] = 0L;
78 ((unsigned long*)blocks)[191] = 0L;
79 i += 16;
80 }
81 #else
82 memset(blocks, 0, sizeof(DCTELEM)*6*64);
83 #endif
84 }
85
86 /* same as above, when dcbzl clear a whole 128B cache line
87 i.e. the PPC970 aka G5 */
88 #if HAVE_DCBZL
89 static void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
90 {
91 register int misal = ((unsigned long)blocks & 0x0000007f);
92 register int i = 0;
93 #if 1
94 if (misal) {
95 // we could probably also optimize this case,
96 // but there's not much point as the machines
97 // aren't available yet (2003-06-26)
98 memset(blocks, 0, sizeof(DCTELEM)*6*64);
99 }
100 else
101 for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
102 __asm__ volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory");
103 }
104 #else
105 memset(blocks, 0, sizeof(DCTELEM)*6*64);
106 #endif
107 }
108 #else
109 static void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
110 {
111 memset(blocks, 0, sizeof(DCTELEM)*6*64);
112 }
113 #endif
114
115 #if HAVE_DCBZL
116 /* check dcbz report how many bytes are set to 0 by dcbz */
117 /* update 24/06/2003 : replace dcbz by dcbzl to get
118 the intended effect (Apple "fixed" dcbz)
119 unfortunately this cannot be used unless the assembler
120 knows about dcbzl ... */
121 static long check_dcbzl_effect(void)
122 {
123 register char *fakedata = av_malloc(1024);
124 register char *fakedata_middle;
125 register long zero = 0;
126 register long i = 0;
127 long count = 0;
128
129 if (!fakedata) {
130 return 0L;
131 }
132
133 fakedata_middle = (fakedata + 512);
134
135 memset(fakedata, 0xFF, 1024);
136
137 /* below the constraint "b" seems to mean "Address base register"
138 in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */
139 __asm__ volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero));
140
141 for (i = 0; i < 1024 ; i ++) {
142 if (fakedata[i] == (char)0)
143 count++;
144 }
145
146 av_free(fakedata);
147
148 return count;
149 }
150 #else
151 static long check_dcbzl_effect(void)
152 {
153 return 0;
154 }
155 #endif
156
157 static void prefetch_ppc(void *mem, int stride, int h)
158 {
159 register const uint8_t *p = mem;
160 do {
161 __asm__ volatile ("dcbt 0,%0" : : "r" (p));
162 p+= stride;
163 } while(--h);
164 }
165
166 void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
167 {
168 // Common optimizations whether AltiVec is available or not
169 c->prefetch = prefetch_ppc;
170 switch (check_dcbzl_effect()) {
171 case 32:
172 c->clear_blocks = clear_blocks_dcbz32_ppc;
173 break;
174 case 128:
175 c->clear_blocks = clear_blocks_dcbz128_ppc;
176 break;
177 default:
178 break;
179 }
180
181 #if HAVE_ALTIVEC
182 if(CONFIG_H264_DECODER) dsputil_h264_init_ppc(c, avctx);
183
184 if (has_altivec()) {
185 mm_flags |= FF_MM_ALTIVEC;
186
187 dsputil_init_altivec(c, avctx);
188 if(CONFIG_VC1_DECODER)
189 vc1dsp_init_altivec(c, avctx);
190 float_init_altivec(c, avctx);
191 int_init_altivec(c, avctx);
192 c->gmc1 = gmc1_altivec;
193
194 #if CONFIG_ENCODERS
195 if (avctx->dct_algo == FF_DCT_AUTO ||
196 avctx->dct_algo == FF_DCT_ALTIVEC) {
197 c->fdct = fdct_altivec;
198 }
199 #endif //CONFIG_ENCODERS
200
201 if (avctx->lowres==0) {
202 if ((avctx->idct_algo == FF_IDCT_AUTO) ||
203 (avctx->idct_algo == FF_IDCT_ALTIVEC)) {
204 c->idct_put = idct_put_altivec;
205 c->idct_add = idct_add_altivec;
206 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
207 }else if((CONFIG_VP3_DECODER || CONFIG_VP5_DECODER || CONFIG_VP6_DECODER) &&
208 avctx->idct_algo==FF_IDCT_VP3){
209 c->idct_put = ff_vp3_idct_put_altivec;
210 c->idct_add = ff_vp3_idct_add_altivec;
211 c->idct = ff_vp3_idct_altivec;
212 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
213 }
214 }
215
216 }
217 #endif /* HAVE_ALTIVEC */
218 }