libavcodec/ppc/dsputil_ppc.c

   1 /*
   2  * Copyright (c) 2002 Brian Foley
   3  * Copyright (c) 2002 Dieter Shirley
   4  *
   5  * This library is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU Lesser General Public
   7  * License as published by the Free Software Foundation; either
   8  * version 2 of the License, or (at your option) any later version.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include "../dsputil.h"
  21
  22 #include "dsputil_ppc.h"
  23
  24 #ifdef HAVE_ALTIVEC
  25 #include "dsputil_altivec.h"
  26 #endif
  27
  28 extern void idct_put_altivec(uint8_t *dest, int line_size, int16_t *block);
  29 extern void idct_add_altivec(uint8_t *dest, int line_size, int16_t *block);
  30
  31 int mm_flags = 0;
  32
  33 int mm_support(void)
  34 {
  35     int result = 0;
  36 #if HAVE_ALTIVEC
  37     if (has_altivec()) {
  38         result |= MM_ALTIVEC;
  39     }
  40 #endif /* result */
  41     return result;
  42 }
  43
  44 #ifdef POWERPC_TBL_PERFORMANCE_REPORT
  45 unsigned long long perfdata[powerpc_perf_total][powerpc_data_total];
  46 /* list below must match enum in dsputil_ppc.h */
  47 static unsigned char* perfname[] = {
  48   "fft_calc_altivec",
  49   "gmc1_altivec",
  50   "dct_unquantize_h263_altivec",
  51   "idct_add_altivec",
  52   "idct_put_altivec",
  53   "put_pixels16_altivec",
  54   "avg_pixels16_altivec",
  55   "avg_pixels8_altivec",
  56   "put_pixels8_xy2_altivec",
  57   "put_no_rnd_pixels8_xy2_altivec",
  58   "put_pixels16_xy2_altivec",
  59   "put_no_rnd_pixels16_xy2_altivec",
  60   "clear_blocks_dcbz32_ppc",
  61   "clear_blocks_dcbz128_ppc"
  62 };
  63 #ifdef POWERPC_PERF_USE_PMC
  64 unsigned long long perfdata_miss[powerpc_perf_total][powerpc_data_total];
  65 #endif
  66 #include <stdio.h>
  67 #endif
  68
  69 #ifdef POWERPC_TBL_PERFORMANCE_REPORT
  70 void powerpc_display_perf_report(void)
  71 {
  72   int i;
  73 #ifndef POWERPC_PERF_USE_PMC
  74   fprintf(stderr, "PowerPC performance report\n Values are from the Time Base register, and represent 4 bus cycles.\n");
  75 #else /* POWERPC_PERF_USE_PMC */
  76   fprintf(stderr, "PowerPC performance report\n Values are from the PMC registers, and represent whatever the registers are set to record.\n");
  77 #endif /* POWERPC_PERF_USE_PMC */
  78   for(i = 0 ; i < powerpc_perf_total ; i++)
  79   {
  80     if (perfdata[i][powerpc_data_num] != (unsigned long long)0)
  81       fprintf(stderr, " Function \"%s\" (pmc1):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n",
  82               perfname[i],
  83               perfdata[i][powerpc_data_min],
  84               perfdata[i][powerpc_data_max],
  85               (double)perfdata[i][powerpc_data_sum] /
  86               (double)perfdata[i][powerpc_data_num],
  87               perfdata[i][powerpc_data_num]);
  88 #ifdef POWERPC_PERF_USE_PMC
  89     if (perfdata_miss[i][powerpc_data_num] != (unsigned long long)0)
  90       fprintf(stderr, " Function \"%s\" (pmc2):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n",
  91               perfname[i],
  92               perfdata_miss[i][powerpc_data_min],
  93               perfdata_miss[i][powerpc_data_max],
  94               (double)perfdata_miss[i][powerpc_data_sum] /
  95               (double)perfdata_miss[i][powerpc_data_num],
  96               perfdata_miss[i][powerpc_data_num]);
  97 #endif
  98   }
  99 }
 100 #endif /* POWERPC_TBL_PERFORMANCE_REPORT */
 101
 102 /* ***** WARNING ***** WARNING ***** WARNING ***** */
 103 /*
 104   clear_blocks_dcbz32_ppc will not work properly
 105   on PowerPC processors with a cache line size
 106   not equal to 32 bytes.
 107   Fortunately all processor used by Apple up to
 108   at least the 7450 (aka second generation G4)
 109   use 32 bytes cache line.
 110   This is due to the use of the 'dcbz' instruction.
 111   It simply clear to zero a single cache line,
 112   so you need to know the cache line size to use it !
 113   It's absurd, but it's fast...
 114
 115   update 24/06/2003 : Apple released yesterday the G5,
 116   with a PPC970. cache line size : 128 bytes. Oups.
 117   The semantic of dcbz was changed, it always clear
 118   32 bytes. so the function below will work, but will
 119   be slow. So I fixed check_dcbz_effect to use dcbzl,
 120   which is defined to clear a cache line (as dcbz before).
 121   So we still can distinguish, and use dcbz (32 bytes)
 122   or dcbzl (one cache line) as required.
 123
 124   see <http://developer.apple.com/technotes/tn/tn2087.html>
 125   and <http://developer.apple.com/technotes/tn/tn2086.html>
 126 */
 127 void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
 128 {
 129 POWERPC_TBL_DECLARE(powerpc_clear_blocks_dcbz32, 1);
 130     register int misal = ((unsigned long)blocks & 0x00000010);
 131     register int i = 0;
 132 POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz32, 1);
 133 #if 1
 134     if (misal) {
 135       ((unsigned long*)blocks)[0] = 0L;
 136       ((unsigned long*)blocks)[1] = 0L;
 137       ((unsigned long*)blocks)[2] = 0L;
 138       ((unsigned long*)blocks)[3] = 0L;
 139       i += 16;
 140     }
 141     for ( ; i < sizeof(DCTELEM)*6*64 ; i += 32) {
 142       asm volatile("dcbz %0,%1" : : "r" (i), "r" (blocks) : "memory");
 143     }
 144     if (misal) {
 145       ((unsigned long*)blocks)[188] = 0L;
 146       ((unsigned long*)blocks)[189] = 0L;
 147       ((unsigned long*)blocks)[190] = 0L;
 148       ((unsigned long*)blocks)[191] = 0L;
 149       i += 16;
 150     }
 151 #else
 152     memset(blocks, 0, sizeof(DCTELEM)*6*64);
 153 #endif
 154 POWERPC_TBL_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1);
 155 }
 156
 157 /* same as above, when dcbzl clear a whole 128B cache line
 158    i.e. the PPC970 aka G5 */
 159 #ifndef NO_DCBZL
 160 void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
 161 {
 162 POWERPC_TBL_DECLARE(powerpc_clear_blocks_dcbz128, 1);
 163     register int misal = ((unsigned long)blocks & 0x0000007f);
 164     register int i = 0;
 165 POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz128, 1);
 166 #if 1
 167  if (misal) {
 168    // we could probably also optimize this case,
 169    // but there's not much point as the machines
 170    // aren't available yet (2003-06-26)
 171       memset(blocks, 0, sizeof(DCTELEM)*6*64);
 172     }
 173     else
 174       for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
 175         asm volatile("dcbzl %0,%1" : : "r" (i), "r" (blocks) : "memory");
 176       }
 177 #else
 178     memset(blocks, 0, sizeof(DCTELEM)*6*64);
 179 #endif
 180 POWERPC_TBL_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1);
 181 }
 182 #else
 183 void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
 184 {
 185   memset(blocks, 0, sizeof(DCTELEM)*6*64);
 186 }
 187 #endif
 188
 189 #ifndef NO_DCBZL
 190 /* check dcbz report how many bytes are set to 0 by dcbz */
 191 /* update 24/06/2003 : replace dcbz by dcbzl to get
 192    the intended effect (Apple "fixed" dcbz)
 193    unfortunately this cannot be used unless the assembler
 194    knows about dcbzl ... */
 195 long check_dcbzl_effect(void)
 196 {
 197   register char *fakedata = (char*)av_malloc(1024);
 198   register char *fakedata_middle;
 199   register long zero = 0;
 200   register long i = 0;
 201   long count = 0;
 202
 203   if (!fakedata)
 204   {
 205     return 0L;
 206   }
 207
 208   fakedata_middle = (fakedata + 512);
 209
 210   memset(fakedata, 0xFF, 1024);
 211
 212   asm volatile("dcbzl %0, %1" : : "r" (fakedata_middle), "r" (zero));
 213
 214   for (i = 0; i < 1024 ; i ++)
 215   {
 216     if (fakedata[i] == (char)0)
 217       count++;
 218   }
 219
 220   av_free(fakedata);
 221
 222   return count;
 223 }
 224 #else
 225 long check_dcbzl_effect(void)
 226 {
 227   return 0;
 228 }
 229 #endif
 230
 231 void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
 232 {
 233     // Common optimizations whether Altivec is available or not
 234
 235   switch (check_dcbzl_effect()) {
 236   case 32:
 237     c->clear_blocks = clear_blocks_dcbz32_ppc;
 238     break;
 239   case 128:
 240     c->clear_blocks = clear_blocks_dcbz128_ppc;
 241     break;
 242   default:
 243     break;
 244   }
 245
 246 #if HAVE_ALTIVEC
 247     if (has_altivec()) {
 248         mm_flags |= MM_ALTIVEC;
 249
 250         // Altivec specific optimisations
 251         c->pix_abs16x16_x2 = pix_abs16x16_x2_altivec;
 252         c->pix_abs16x16_y2 = pix_abs16x16_y2_altivec;
 253         c->pix_abs16x16_xy2 = pix_abs16x16_xy2_altivec;
 254         c->pix_abs16x16 = pix_abs16x16_altivec;
 255         c->pix_abs8x8 = pix_abs8x8_altivec;
 256         c->sad[0]= sad16x16_altivec;
 257         c->sad[1]= sad8x8_altivec;
 258         c->pix_norm1 = pix_norm1_altivec;
 259         c->sse[1]= sse8_altivec;
 260         c->sse[0]= sse16_altivec;
 261         c->pix_sum = pix_sum_altivec;
 262         c->diff_pixels = diff_pixels_altivec;
 263         c->get_pixels = get_pixels_altivec;
 264 // next one disabled as it's untested.
 265 #if 0
 266         c->add_bytes= add_bytes_altivec;
 267 #endif /* 0 */
 268         c->put_pixels_tab[0][0] = put_pixels16_altivec;
 269         c->avg_pixels_tab[0][0] = avg_pixels16_altivec;
 270 // next one disabled as it's untested.
 271 #if 0
 272         c->avg_pixels_tab[1][0] = avg_pixels8_altivec;
 273 #endif /* 0 */
 274         c->put_pixels_tab[1][3] = put_pixels8_xy2_altivec;
 275         c->put_no_rnd_pixels_tab[1][3] = put_no_rnd_pixels8_xy2_altivec;
 276         c->put_pixels_tab[0][3] = put_pixels16_xy2_altivec;
 277         c->put_no_rnd_pixels_tab[0][3] = put_no_rnd_pixels16_xy2_altivec;
 278
 279         c->gmc1 = gmc1_altivec;
 280
 281         if ((avctx->idct_algo == FF_IDCT_AUTO) ||
 282                 (avctx->idct_algo == FF_IDCT_ALTIVEC))
 283         {
 284             c->idct_put = idct_put_altivec;
 285             c->idct_add = idct_add_altivec;
 286 #ifndef ALTIVEC_USE_REFERENCE_C_CODE
 287             c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
 288 #else /* ALTIVEC_USE_REFERENCE_C_CODE */
 289             c->idct_permutation_type = FF_NO_IDCT_PERM;
 290 #endif /* ALTIVEC_USE_REFERENCE_C_CODE */
 291         }
 292
 293 #ifdef POWERPC_TBL_PERFORMANCE_REPORT
 294         {
 295           int i;
 296           for (i = 0 ; i < powerpc_perf_total ; i++)
 297           {
 298             perfdata[i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFF;
 299             perfdata[i][powerpc_data_max] = 0x0000000000000000;
 300             perfdata[i][powerpc_data_sum] = 0x0000000000000000;
 301             perfdata[i][powerpc_data_num] = 0x0000000000000000;
 302 #ifdef POWERPC_PERF_USE_PMC
 303             perfdata_miss[i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFF;
 304             perfdata_miss[i][powerpc_data_max] = 0x0000000000000000;
 305             perfdata_miss[i][powerpc_data_sum] = 0x0000000000000000;
 306             perfdata_miss[i][powerpc_data_num] = 0x0000000000000000;
 307 #endif /* POWERPC_PERF_USE_PMC */
 308           }
 309         }
 310 #endif /* POWERPC_TBL_PERFORMANCE_REPORT */
 311     } else
 312 #endif /* HAVE_ALTIVEC */
 313     {
 314         // Non-AltiVec PPC optimisations
 315
 316         // ... pending ...
 317     }
 318 }