cf0ac39de31b8f0afbfa6636954667b8c238d86f
[libav.git] / libavcodec / ppc / dsputil_ppc.c
1 /*
2 * Copyright (c) 2002 Brian Foley
3 * Copyright (c) 2002 Dieter Shirley
4 * Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org>
5 *
6 * This file is part of FFmpeg.
7 *
8 * FFmpeg is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * FFmpeg is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with FFmpeg; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23 #include "libavcodec/dsputil.h"
24
25 #include "dsputil_ppc.h"
26
27 #include "dsputil_altivec.h"
28
29 int mm_flags = 0;
30
31 int mm_support(void)
32 {
33 int result = 0;
34 #if HAVE_ALTIVEC
35 if (has_altivec()) {
36 result |= FF_MM_ALTIVEC;
37 }
38 #endif /* result */
39 return result;
40 }
41
42 #if CONFIG_POWERPC_PERF
43 unsigned long long perfdata[POWERPC_NUM_PMC_ENABLED][powerpc_perf_total][powerpc_data_total];
44 /* list below must match enum in dsputil_ppc.h */
45 static unsigned char* perfname[] = {
46 "ff_fft_calc_altivec",
47 "gmc1_altivec",
48 "dct_unquantize_h263_altivec",
49 "fdct_altivec",
50 "idct_add_altivec",
51 "idct_put_altivec",
52 "put_pixels16_altivec",
53 "avg_pixels16_altivec",
54 "avg_pixels8_altivec",
55 "put_pixels8_xy2_altivec",
56 "put_no_rnd_pixels8_xy2_altivec",
57 "put_pixels16_xy2_altivec",
58 "put_no_rnd_pixels16_xy2_altivec",
59 "hadamard8_diff8x8_altivec",
60 "hadamard8_diff16_altivec",
61 "avg_pixels8_xy2_altivec",
62 "clear_blocks_dcbz32_ppc",
63 "clear_blocks_dcbz128_ppc",
64 "put_h264_chroma_mc8_altivec",
65 "avg_h264_chroma_mc8_altivec",
66 "put_h264_qpel16_h_lowpass_altivec",
67 "avg_h264_qpel16_h_lowpass_altivec",
68 "put_h264_qpel16_v_lowpass_altivec",
69 "avg_h264_qpel16_v_lowpass_altivec",
70 "put_h264_qpel16_hv_lowpass_altivec",
71 "avg_h264_qpel16_hv_lowpass_altivec",
72 ""
73 };
74 #include <stdio.h>
75 #endif
76
77 #if CONFIG_POWERPC_PERF
78 void powerpc_display_perf_report(void)
79 {
80 int i, j;
81 av_log(NULL, AV_LOG_INFO, "PowerPC performance report\n Values are from the PMC registers, and represent whatever the registers are set to record.\n");
82 for(i = 0 ; i < powerpc_perf_total ; i++) {
83 for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++) {
84 if (perfdata[j][i][powerpc_data_num] != (unsigned long long)0)
85 av_log(NULL, AV_LOG_INFO,
86 " Function \"%s\" (pmc%d):\n\tmin: %"PRIu64"\n\tmax: %"PRIu64"\n\tavg: %1.2lf (%"PRIu64")\n",
87 perfname[i],
88 j+1,
89 perfdata[j][i][powerpc_data_min],
90 perfdata[j][i][powerpc_data_max],
91 (double)perfdata[j][i][powerpc_data_sum] /
92 (double)perfdata[j][i][powerpc_data_num],
93 perfdata[j][i][powerpc_data_num]);
94 }
95 }
96 }
97 #endif /* CONFIG_POWERPC_PERF */
98
99 /* ***** WARNING ***** WARNING ***** WARNING ***** */
100 /*
101 clear_blocks_dcbz32_ppc will not work properly on PowerPC processors with a
102 cache line size not equal to 32 bytes.
103 Fortunately all processor used by Apple up to at least the 7450 (aka second
104 generation G4) use 32 bytes cache line.
105 This is due to the use of the 'dcbz' instruction. It simply clear to zero a
106 single cache line, so you need to know the cache line size to use it !
107 It's absurd, but it's fast...
108
109 update 24/06/2003 : Apple released yesterday the G5, with a PPC970. cache line
110 size: 128 bytes. Oups.
111 The semantic of dcbz was changed, it always clear 32 bytes. so the function
112 below will work, but will be slow. So I fixed check_dcbz_effect to use dcbzl,
113 which is defined to clear a cache line (as dcbz before). So we still can
114 distinguish, and use dcbz (32 bytes) or dcbzl (one cache line) as required.
115
116 see <http://developer.apple.com/technotes/tn/tn2087.html>
117 and <http://developer.apple.com/technotes/tn/tn2086.html>
118 */
119 static void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
120 {
121 POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz32, 1);
122 register int misal = ((unsigned long)blocks & 0x00000010);
123 register int i = 0;
124 POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz32, 1);
125 #if 1
126 if (misal) {
127 ((unsigned long*)blocks)[0] = 0L;
128 ((unsigned long*)blocks)[1] = 0L;
129 ((unsigned long*)blocks)[2] = 0L;
130 ((unsigned long*)blocks)[3] = 0L;
131 i += 16;
132 }
133 for ( ; i < sizeof(DCTELEM)*6*64-31 ; i += 32) {
134 __asm__ volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory");
135 }
136 if (misal) {
137 ((unsigned long*)blocks)[188] = 0L;
138 ((unsigned long*)blocks)[189] = 0L;
139 ((unsigned long*)blocks)[190] = 0L;
140 ((unsigned long*)blocks)[191] = 0L;
141 i += 16;
142 }
143 #else
144 memset(blocks, 0, sizeof(DCTELEM)*6*64);
145 #endif
146 POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1);
147 }
148
149 /* same as above, when dcbzl clear a whole 128B cache line
150 i.e. the PPC970 aka G5 */
151 #if HAVE_DCBZL
152 static void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
153 {
154 POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz128, 1);
155 register int misal = ((unsigned long)blocks & 0x0000007f);
156 register int i = 0;
157 POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz128, 1);
158 #if 1
159 if (misal) {
160 // we could probably also optimize this case,
161 // but there's not much point as the machines
162 // aren't available yet (2003-06-26)
163 memset(blocks, 0, sizeof(DCTELEM)*6*64);
164 }
165 else
166 for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
167 __asm__ volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory");
168 }
169 #else
170 memset(blocks, 0, sizeof(DCTELEM)*6*64);
171 #endif
172 POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1);
173 }
174 #else
175 static void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
176 {
177 memset(blocks, 0, sizeof(DCTELEM)*6*64);
178 }
179 #endif
180
181 #if HAVE_DCBZL
182 /* check dcbz report how many bytes are set to 0 by dcbz */
183 /* update 24/06/2003 : replace dcbz by dcbzl to get
184 the intended effect (Apple "fixed" dcbz)
185 unfortunately this cannot be used unless the assembler
186 knows about dcbzl ... */
187 static long check_dcbzl_effect(void)
188 {
189 register char *fakedata = av_malloc(1024);
190 register char *fakedata_middle;
191 register long zero = 0;
192 register long i = 0;
193 long count = 0;
194
195 if (!fakedata) {
196 return 0L;
197 }
198
199 fakedata_middle = (fakedata + 512);
200
201 memset(fakedata, 0xFF, 1024);
202
203 /* below the constraint "b" seems to mean "Address base register"
204 in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */
205 __asm__ volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero));
206
207 for (i = 0; i < 1024 ; i ++) {
208 if (fakedata[i] == (char)0)
209 count++;
210 }
211
212 av_free(fakedata);
213
214 return count;
215 }
216 #else
217 static long check_dcbzl_effect(void)
218 {
219 return 0;
220 }
221 #endif
222
223 static void prefetch_ppc(void *mem, int stride, int h)
224 {
225 register const uint8_t *p = mem;
226 do {
227 __asm__ volatile ("dcbt 0,%0" : : "r" (p));
228 p+= stride;
229 } while(--h);
230 }
231
232 void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
233 {
234 // Common optimizations whether AltiVec is available or not
235 c->prefetch = prefetch_ppc;
236 switch (check_dcbzl_effect()) {
237 case 32:
238 c->clear_blocks = clear_blocks_dcbz32_ppc;
239 break;
240 case 128:
241 c->clear_blocks = clear_blocks_dcbz128_ppc;
242 break;
243 default:
244 break;
245 }
246
247 #if HAVE_ALTIVEC
248 if(CONFIG_H264_DECODER) dsputil_h264_init_ppc(c, avctx);
249
250 if (has_altivec()) {
251 mm_flags |= FF_MM_ALTIVEC;
252
253 dsputil_init_altivec(c, avctx);
254 if(CONFIG_VC1_DECODER)
255 vc1dsp_init_altivec(c, avctx);
256 float_init_altivec(c, avctx);
257 int_init_altivec(c, avctx);
258 c->gmc1 = gmc1_altivec;
259
260 #if CONFIG_ENCODERS
261 if (avctx->dct_algo == FF_DCT_AUTO ||
262 avctx->dct_algo == FF_DCT_ALTIVEC) {
263 c->fdct = fdct_altivec;
264 }
265 #endif //CONFIG_ENCODERS
266
267 if (avctx->lowres==0) {
268 if ((avctx->idct_algo == FF_IDCT_AUTO) ||
269 (avctx->idct_algo == FF_IDCT_ALTIVEC)) {
270 c->idct_put = idct_put_altivec;
271 c->idct_add = idct_add_altivec;
272 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
273 }else if((CONFIG_VP3_DECODER || CONFIG_VP5_DECODER || CONFIG_VP6_DECODER) &&
274 avctx->idct_algo==FF_IDCT_VP3){
275 c->idct_put = ff_vp3_idct_put_altivec;
276 c->idct_add = ff_vp3_idct_add_altivec;
277 c->idct = ff_vp3_idct_altivec;
278 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
279 }
280 }
281
282 #if CONFIG_POWERPC_PERF
283 {
284 int i, j;
285 for (i = 0 ; i < powerpc_perf_total ; i++) {
286 for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++) {
287 perfdata[j][i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFFULL;
288 perfdata[j][i][powerpc_data_max] = 0x0000000000000000ULL;
289 perfdata[j][i][powerpc_data_sum] = 0x0000000000000000ULL;
290 perfdata[j][i][powerpc_data_num] = 0x0000000000000000ULL;
291 }
292 }
293 }
294 #endif /* CONFIG_POWERPC_PERF */
295 }
296 #endif /* HAVE_ALTIVEC */
297 }