01c0a12b153e30e36784bc079bf862c2fac6efbb
[libav.git] / libavcodec / ppc / idct_altivec.c
1 /*
2 * Copyright (c) 2001 Michel Lespinasse
3 *
4 * This file is part of FFmpeg.
5 *
6 * FFmpeg is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * FFmpeg is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with FFmpeg; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21 /*
22 * NOTE: This code is based on GPL code from the libmpeg2 project. The
23 * author, Michel Lespinasses, has given explicit permission to release
24 * under LGPL as part of ffmpeg.
25 *
26 */
27
28 /*
29 * FFMpeg integration by Dieter Shirley
30 *
31 * This file is a direct copy of the altivec idct module from the libmpeg2
32 * project. I've deleted all of the libmpeg2 specific code, renamed the functions and
33 * re-ordered the function parameters. The only change to the IDCT function
34 * itself was to factor out the partial transposition, and to perform a full
35 * transpose at the end of the function.
36 */
37
38
39 #include <stdlib.h> /* malloc(), free() */
40 #include <string.h>
41 #include "dsputil.h"
42
43 #include "gcc_fixes.h"
44
45 #include "dsputil_altivec.h"
46
47 #define vector_s16_t vector signed short
48 #define const_vector_s16_t const vector signed short
49 #define vector_u16_t vector unsigned short
50 #define vector_s8_t vector signed char
51 #define vector_u8_t vector unsigned char
52 #define vector_s32_t vector signed int
53 #define vector_u32_t vector unsigned int
54
55 #define IDCT_HALF \
56 /* 1st stage */ \
57 t1 = vec_mradds (a1, vx7, vx1 ); \
58 t8 = vec_mradds (a1, vx1, vec_subs (zero, vx7)); \
59 t7 = vec_mradds (a2, vx5, vx3); \
60 t3 = vec_mradds (ma2, vx3, vx5); \
61 \
62 /* 2nd stage */ \
63 t5 = vec_adds (vx0, vx4); \
64 t0 = vec_subs (vx0, vx4); \
65 t2 = vec_mradds (a0, vx6, vx2); \
66 t4 = vec_mradds (a0, vx2, vec_subs (zero, vx6)); \
67 t6 = vec_adds (t8, t3); \
68 t3 = vec_subs (t8, t3); \
69 t8 = vec_subs (t1, t7); \
70 t1 = vec_adds (t1, t7); \
71 \
72 /* 3rd stage */ \
73 t7 = vec_adds (t5, t2); \
74 t2 = vec_subs (t5, t2); \
75 t5 = vec_adds (t0, t4); \
76 t0 = vec_subs (t0, t4); \
77 t4 = vec_subs (t8, t3); \
78 t3 = vec_adds (t8, t3); \
79 \
80 /* 4th stage */ \
81 vy0 = vec_adds (t7, t1); \
82 vy7 = vec_subs (t7, t1); \
83 vy1 = vec_mradds (c4, t3, t5); \
84 vy6 = vec_mradds (mc4, t3, t5); \
85 vy2 = vec_mradds (c4, t4, t0); \
86 vy5 = vec_mradds (mc4, t4, t0); \
87 vy3 = vec_adds (t2, t6); \
88 vy4 = vec_subs (t2, t6);
89
90
91 #define IDCT \
92 vector_s16_t vx0, vx1, vx2, vx3, vx4, vx5, vx6, vx7; \
93 vector_s16_t vy0, vy1, vy2, vy3, vy4, vy5, vy6, vy7; \
94 vector_s16_t a0, a1, a2, ma2, c4, mc4, zero, bias; \
95 vector_s16_t t0, t1, t2, t3, t4, t5, t6, t7, t8; \
96 vector_u16_t shift; \
97 \
98 c4 = vec_splat (constants[0], 0); \
99 a0 = vec_splat (constants[0], 1); \
100 a1 = vec_splat (constants[0], 2); \
101 a2 = vec_splat (constants[0], 3); \
102 mc4 = vec_splat (constants[0], 4); \
103 ma2 = vec_splat (constants[0], 5); \
104 bias = (vector_s16_t)vec_splat ((vector_s32_t)constants[0], 3); \
105 \
106 zero = vec_splat_s16 (0); \
107 shift = vec_splat_u16 (4); \
108 \
109 vx0 = vec_mradds (vec_sl (block[0], shift), constants[1], zero); \
110 vx1 = vec_mradds (vec_sl (block[1], shift), constants[2], zero); \
111 vx2 = vec_mradds (vec_sl (block[2], shift), constants[3], zero); \
112 vx3 = vec_mradds (vec_sl (block[3], shift), constants[4], zero); \
113 vx4 = vec_mradds (vec_sl (block[4], shift), constants[1], zero); \
114 vx5 = vec_mradds (vec_sl (block[5], shift), constants[4], zero); \
115 vx6 = vec_mradds (vec_sl (block[6], shift), constants[3], zero); \
116 vx7 = vec_mradds (vec_sl (block[7], shift), constants[2], zero); \
117 \
118 IDCT_HALF \
119 \
120 vx0 = vec_mergeh (vy0, vy4); \
121 vx1 = vec_mergel (vy0, vy4); \
122 vx2 = vec_mergeh (vy1, vy5); \
123 vx3 = vec_mergel (vy1, vy5); \
124 vx4 = vec_mergeh (vy2, vy6); \
125 vx5 = vec_mergel (vy2, vy6); \
126 vx6 = vec_mergeh (vy3, vy7); \
127 vx7 = vec_mergel (vy3, vy7); \
128 \
129 vy0 = vec_mergeh (vx0, vx4); \
130 vy1 = vec_mergel (vx0, vx4); \
131 vy2 = vec_mergeh (vx1, vx5); \
132 vy3 = vec_mergel (vx1, vx5); \
133 vy4 = vec_mergeh (vx2, vx6); \
134 vy5 = vec_mergel (vx2, vx6); \
135 vy6 = vec_mergeh (vx3, vx7); \
136 vy7 = vec_mergel (vx3, vx7); \
137 \
138 vx0 = vec_adds (vec_mergeh (vy0, vy4), bias); \
139 vx1 = vec_mergel (vy0, vy4); \
140 vx2 = vec_mergeh (vy1, vy5); \
141 vx3 = vec_mergel (vy1, vy5); \
142 vx4 = vec_mergeh (vy2, vy6); \
143 vx5 = vec_mergel (vy2, vy6); \
144 vx6 = vec_mergeh (vy3, vy7); \
145 vx7 = vec_mergel (vy3, vy7); \
146 \
147 IDCT_HALF \
148 \
149 shift = vec_splat_u16 (6); \
150 vx0 = vec_sra (vy0, shift); \
151 vx1 = vec_sra (vy1, shift); \
152 vx2 = vec_sra (vy2, shift); \
153 vx3 = vec_sra (vy3, shift); \
154 vx4 = vec_sra (vy4, shift); \
155 vx5 = vec_sra (vy5, shift); \
156 vx6 = vec_sra (vy6, shift); \
157 vx7 = vec_sra (vy7, shift);
158
159
160 static const_vector_s16_t constants[5] = {
161 (vector_s16_t) AVV(23170, 13573, 6518, 21895, -23170, -21895, 32, 31),
162 (vector_s16_t) AVV(16384, 22725, 21407, 19266, 16384, 19266, 21407, 22725),
163 (vector_s16_t) AVV(22725, 31521, 29692, 26722, 22725, 26722, 29692, 31521),
164 (vector_s16_t) AVV(21407, 29692, 27969, 25172, 21407, 25172, 27969, 29692),
165 (vector_s16_t) AVV(19266, 26722, 25172, 22654, 19266, 22654, 25172, 26722)
166 };
167
168 void idct_put_altivec(uint8_t* dest, int stride, vector_s16_t* block)
169 {
170 POWERPC_PERF_DECLARE(altivec_idct_put_num, 1);
171 vector_u8_t tmp;
172
173 #ifdef CONFIG_POWERPC_PERF
174 POWERPC_PERF_START_COUNT(altivec_idct_put_num, 1);
175 #endif
176 IDCT
177
178 #define COPY(dest,src) \
179 tmp = vec_packsu (src, src); \
180 vec_ste ((vector_u32_t)tmp, 0, (unsigned int *)dest); \
181 vec_ste ((vector_u32_t)tmp, 4, (unsigned int *)dest);
182
183 COPY (dest, vx0) dest += stride;
184 COPY (dest, vx1) dest += stride;
185 COPY (dest, vx2) dest += stride;
186 COPY (dest, vx3) dest += stride;
187 COPY (dest, vx4) dest += stride;
188 COPY (dest, vx5) dest += stride;
189 COPY (dest, vx6) dest += stride;
190 COPY (dest, vx7)
191
192 POWERPC_PERF_STOP_COUNT(altivec_idct_put_num, 1);
193 }
194
195 void idct_add_altivec(uint8_t* dest, int stride, vector_s16_t* block)
196 {
197 POWERPC_PERF_DECLARE(altivec_idct_add_num, 1);
198 vector_u8_t tmp;
199 vector_s16_t tmp2, tmp3;
200 vector_u8_t perm0;
201 vector_u8_t perm1;
202 vector_u8_t p0, p1, p;
203
204 #ifdef CONFIG_POWERPC_PERF
205 POWERPC_PERF_START_COUNT(altivec_idct_add_num, 1);
206 #endif
207
208 IDCT
209
210 p0 = vec_lvsl (0, dest);
211 p1 = vec_lvsl (stride, dest);
212 p = vec_splat_u8 (-1);
213 perm0 = vec_mergeh (p, p0);
214 perm1 = vec_mergeh (p, p1);
215
216 #define ADD(dest,src,perm) \
217 /* *(uint64_t *)&tmp = *(uint64_t *)dest; */ \
218 tmp = vec_ld (0, dest); \
219 tmp2 = (vector_s16_t)vec_perm (tmp, (vector_u8_t)zero, perm); \
220 tmp3 = vec_adds (tmp2, src); \
221 tmp = vec_packsu (tmp3, tmp3); \
222 vec_ste ((vector_u32_t)tmp, 0, (unsigned int *)dest); \
223 vec_ste ((vector_u32_t)tmp, 4, (unsigned int *)dest);
224
225 ADD (dest, vx0, perm0) dest += stride;
226 ADD (dest, vx1, perm1) dest += stride;
227 ADD (dest, vx2, perm0) dest += stride;
228 ADD (dest, vx3, perm1) dest += stride;
229 ADD (dest, vx4, perm0) dest += stride;
230 ADD (dest, vx5, perm1) dest += stride;
231 ADD (dest, vx6, perm0) dest += stride;
232 ADD (dest, vx7, perm1)
233
234 POWERPC_PERF_STOP_COUNT(altivec_idct_add_num, 1);
235 }
236